[llvm] r369095 - [RISCV] Lower inline asm constraint A for RISC-V

[Hans Wennborg via llvm-commits]

Merged to release_90 in r369651.

On Fri, Aug 16, 2019 at 12:27 PM Lewis Revill via llvm-commits
<llvm-commits at lists.llvm.org> wrote:
>
> Author: lewis-revill
> Date: Fri Aug 16 03:28:34 2019
> New Revision: 369095
>
> URL: http://llvm.org/viewvc/llvm-project?rev=369095&view=rev
> Log:
> [RISCV] Lower inline asm constraint A for RISC-V
>
> This allows arguments with the constraint A to be lowered to input nodes
> for RISC-V, which implies a memory address stored in a register.
>
> This patch adds the minimal amount of code required to get operands with
> the right constraints to compile.
>
> https://reviews.llvm.org/D54296
>
>
> Modified:
>     llvm/trunk/include/llvm/IR/InlineAsm.h
>     llvm/trunk/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
>     llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp
>     llvm/trunk/lib/Target/RISCV/RISCVISelLowering.h
>     llvm/trunk/test/CodeGen/RISCV/inline-asm.ll
>
> Modified: llvm/trunk/include/llvm/IR/InlineAsm.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/InlineAsm.h?rev=369095&r1=369094&r2=369095&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/IR/InlineAsm.h (original)
> +++ llvm/trunk/include/llvm/IR/InlineAsm.h Fri Aug 16 03:28:34 2019
> @@ -244,6 +244,7 @@ public:
>      Constraint_m,
>      Constraint_o,
>      Constraint_v,
> +    Constraint_A,
>      Constraint_Q,
>      Constraint_R,
>      Constraint_S,
>
> Modified: llvm/trunk/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVISelDAGToDAG.cpp?rev=369095&r1=369094&r2=369095&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/RISCV/RISCVISelDAGToDAG.cpp (original)
> +++ llvm/trunk/lib/Target/RISCV/RISCVISelDAGToDAG.cpp Fri Aug 16 03:28:34 2019
> @@ -179,6 +179,9 @@ bool RISCVDAGToDAGISel::SelectInlineAsmM
>      // operand and need no special handling.
>      OutOps.push_back(Op);
>      return false;
> +  case InlineAsm::Constraint_A:
> +    OutOps.push_back(Op);
> +    return false;
>    default:
>      break;
>    }
>
> Modified: llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp?rev=369095&r1=369094&r2=369095&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp Fri Aug 16 03:28:34 2019
> @@ -2437,6 +2437,8 @@ RISCVTargetLowering::getConstraintType(S
>      case 'J':
>      case 'K':
>        return C_Immediate;
> +    case 'A':
> +      return C_Memory;
>      }
>    }
>    return TargetLowering::getConstraintType(Constraint);
> @@ -2556,6 +2558,21 @@ RISCVTargetLowering::getRegForInlineAsmC
>    return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
>  }
>
> +unsigned
> +RISCVTargetLowering::getInlineAsmMemConstraint(StringRef ConstraintCode) const {
> +  // Currently only support length 1 constraints.
> +  if (ConstraintCode.size() == 1) {
> +    switch (ConstraintCode[0]) {
> +    case 'A':
> +      return InlineAsm::Constraint_A;
> +    default:
> +      break;
> +    }
> +  }
> +
> +  return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
> +}
> +
>  void RISCVTargetLowering::LowerAsmOperandForConstraint(
>      SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
>      SelectionDAG &DAG) const {
>
> Modified: llvm/trunk/lib/Target/RISCV/RISCVISelLowering.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVISelLowering.h?rev=369095&r1=369094&r2=369095&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/RISCV/RISCVISelLowering.h (original)
> +++ llvm/trunk/lib/Target/RISCV/RISCVISelLowering.h Fri Aug 16 03:28:34 2019
> @@ -93,6 +93,9 @@ public:
>    const char *getTargetNodeName(unsigned Opcode) const override;
>
>    ConstraintType getConstraintType(StringRef Constraint) const override;
> +
> +  unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override;
> +
>    std::pair<unsigned, const TargetRegisterClass *>
>    getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
>                                 StringRef Constraint, MVT VT) const override;
>
> Modified: llvm/trunk/test/CodeGen/RISCV/inline-asm.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/inline-asm.ll?rev=369095&r1=369094&r2=369095&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/RISCV/inline-asm.ll (original)
> +++ llvm/trunk/test/CodeGen/RISCV/inline-asm.ll Fri Aug 16 03:28:34 2019
> @@ -150,6 +150,31 @@ define void @constraint_K() nounwind {
>    ret void
>  }
>
> +define void @constraint_A(i8* %a) nounwind {
> +; RV32I-LABEL: constraint_A:
> +; RV32I:       # %bb.0:
> +; RV32I-NEXT:    #APP
> +; RV32I-NEXT:    sb s0, 0(a0)
> +; RV32I-NEXT:    #NO_APP
> +; RV32I-NEXT:    #APP
> +; RV32I-NEXT:    lb s1, 0(a0)
> +; RV32I-NEXT:    #NO_APP
> +; RV32I-NEXT:    ret
> +;
> +; RV64I-LABEL: constraint_A:
> +; RV64I:       # %bb.0:
> +; RV64I-NEXT:    #APP
> +; RV64I-NEXT:    sb s0, 0(a0)
> +; RV64I-NEXT:    #NO_APP
> +; RV64I-NEXT:    #APP
> +; RV64I-NEXT:    lb s1, 0(a0)
> +; RV64I-NEXT:    #NO_APP
> +; RV64I-NEXT:    ret
> +  tail call void asm sideeffect "sb s0, $0", "*A"(i8* %a)
> +  tail call void asm sideeffect "lb s1, $0", "*A"(i8* %a)
> +  ret void
> +}
> +
>  define i32 @modifier_z_zero(i32 %a) nounwind {
>  ; RV32I-LABEL: modifier_z_zero:
>  ; RV32I:       # %bb.0:
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at lists.llvm.org
> https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-commits