[PATCH] D66571: [X86] Add a DAG combine to turn vector (and (srl X, ((1 << C1) - 1)), C2) into (srl (shl (X, C3), C4)) to save a constant pool for the AND mask

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a comment.

We already have these in TLI:

  TLI::shouldFoldConstantShiftPairToMask
  TLI::shouldFoldMaskToVariableShiftPair

ideally we'd keep everything in DAGCombine and have a suitable set of TLI hooks to indicate what codegen we prefer


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  https://reviews.llvm.org/D66571/new/

https://reviews.llvm.org/D66571