[PATCH] D66519: [ARM] Fix lsrl with a 128/256 bit shift amount or a shift of 32

[Dave Green via Phabricator via llvm-commits]

dmgreen accepted this revision.
dmgreen added a comment.
This revision is now accepted and ready to land.

It looks like there's an unrelated change in here, but other than that looks good to me.



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Comment at: llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp:1381
         // pretty baked in right now.
-        MIRBuilder.buildDirectDbgValue(Reg, DI.getVariable(), DI.getExpression());
       }
----------------
This one looks unrelated


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  https://reviews.llvm.org/D66519/new/

https://reviews.llvm.org/D66519