[PATCH] D66547: [X86][BtVer2] Fix latency/throughput of scalar integer MUL instructions.

[Andrea Di Biagio via Phabricator via llvm-commits]

andreadb created this revision.
andreadb added reviewers: RKSimon, craig.topper.
Herald added a subscriber: gbedwell.

Single operand MUL instructions that implicitly set EAX have the following latency/throughput profile (see below):

  imul %cl              # latency: 3cy - uOPs: 1 - 1 JMul
  imul %cx              # latency: 3cy - uOPs: 3 - 3 JMul
  imul %ecx             # latency: 3cy - uOPs: 2 - 2 JMul
  imul %rcx             # latency: 6cy - uOPs: 2 - 4 JMul
  
  mul %cl               # latency: 3cy - uOPs: 1 - 1 JMul
  mul %cx               # latency: 3cy - uOPs: 3 - 3 JMul
  mul %ecx              # latency: 3cy - uOPs: 2 - 2 JMul
  mul %rcx              # latency: 6cy - uOPs: 2 - 4 JMul

Excluding the 64bit variant, which has a latency of 6cy, every other instruction has a latency of 3cy. However, the number of decoded macro-opcodes (as well as the resource cyles) depend on the MUL size.

The two operand MULs have a more predictable profile (see below):

  imul %dx, %dx         # latency: 3cy - uOPs: 1 - 1 JMul
  imul %edx, %edx       # latency: 3cy - uOPs: 1 - 1 JMul
  imul %rdx, %rdx       # latency: 6cy - uOPs: 1 - 4 JMul
  
  imul $3, %dx, %dx     # latency: 4cy - uOPs: 2 - 2 JMul
  imul $3, %ecx, %ecx   # latency: 3cy - uOPs: 1 - 1 JMul
  imul $3, %rdx, %rdx   # latency: 6cy - uOPs: 1 - 4 JMul

This patch updates the values in the scheduling model based on those values.
I had to update quite a few tests because MUL was used in many tests...


https://reviews.llvm.org/D66547

Files:
  lib/Target/X86/X86ScheduleBtVer2.td
  test/tools/llvm-mca/X86/BtVer2/clear-super-register-1.s
  test/tools/llvm-mca/X86/BtVer2/cmpxchg-read-advance.s
  test/tools/llvm-mca/X86/BtVer2/dependency-breaking-sbb-2.s
  test/tools/llvm-mca/X86/BtVer2/partial-reg-update-2.s
  test/tools/llvm-mca/X86/BtVer2/partial-reg-update-4.s
  test/tools/llvm-mca/X86/BtVer2/partial-reg-update-6.s
  test/tools/llvm-mca/X86/BtVer2/partial-reg-update-7.s
  test/tools/llvm-mca/X86/BtVer2/partial-reg-update.s
  test/tools/llvm-mca/X86/BtVer2/read-advance-2.s
  test/tools/llvm-mca/X86/BtVer2/resources-x86_64.s
  test/tools/llvm-mca/X86/intel-syntax.s
  test/tools/llvm-mca/X86/llvm-mca-markers-10.s
  test/tools/llvm-mca/X86/llvm-mca-markers-9.s

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