[PATCH] D66210: [RFC/WIP][RISCV] Enable the machine outliner for RISC-V

[Luís Marques via Phabricator via llvm-commits]

luismarques marked an inline comment as done.
luismarques added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:481
+  RS.enterBasicBlock(MBB);
+  return !RS.isRegUsed(RISCV::X5);
+}
----------------
lewis-revill wrote:
> luismarques wrote:
> > If we are only going to support one possible register for now, shouldn't it be the one least likely to already be in use? Wouldn't that be t6 (x31)?
> That's a sensible suggestion, I was using t0 to match how the save/restore libcalls behave so I presumed there was a good reason for using t0. Don't we also need to think about RV32E here though?
> 
> 
Good point about RV32E. I guess you can either always use `t2` or check the target and use `t6` when available, falling back to `t2` otherwise. If that's not trivial it might be worth checking how hard it would be to dynamically choose the register, like AArch64 does IIRC.


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https://reviews.llvm.org/D66210