[PATCH] D66514: GlobalISel/TableGen: Handle setcc patterns

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added reviewers: dsanders, aemerson, paquette, aditya_nandakumar.
Herald added subscribers: Petar.Avramovic, atanasyan, rovka, nhaehnle, wdng, jvesely, sdardis.

This is a special case because one node maps to two different G_
instructions, and the operand order is changed.

      

This requires duplicating the Predicate enum to avoid a circular build
dependency between TableGen and the IR library. I have a patch which
moves it to support, but it's rather disruptive.

      

This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually
selected for now since it has the SALU and VALU complication to deal
with.


https://reviews.llvm.org/D66514

Files:
  include/llvm/CodeGen/GlobalISel/InstructionSelector.h
  include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
  include/llvm/Target/GlobalISel/SelectionDAGCompat.td
  lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
  lib/Target/AMDGPU/AMDGPURegisterBanks.td
  test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.mir
  test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.s16.mir
  test/CodeGen/Mips/GlobalISel/instruction-select/mul.mir
  test/CodeGen/Mips/GlobalISel/llvm-ir/icmp.ll
  test/CodeGen/Mips/GlobalISel/llvm-ir/mul.ll
  test/TableGen/Common/GlobalISelEmitterCommon.td
  test/TableGen/GlobalISelEmitter-setcc.td
  utils/TableGen/GlobalISelEmitter.cpp

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