[PATCH] D66180: [GlobalISel][CallLowering] Add support for splitting types according to calling conventions

[Amara Emerson via Phabricator via llvm-commits]

aemerson added a comment.

In D66180#1634256 <https://reviews.llvm.org/D66180#1634256>, @arsenm wrote:

> I'm somewhat confused by what the responsibilities of handleAssignments are vs. target code. I already have multiple register breakdowns without this patch in AMDGPU


IIUC calling convention specified register splits should be generic, and it's handled in generic code by SelectionDAG. Whether handleAssignments is the best place for I'm not sure, but I don't think targets should have to deal with this individually. In arm64 I think we already have some target call lowering code that should really be generic.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D66180/new/

https://reviews.llvm.org/D66180