[llvm] r369257 - [RISCV] Don't force absolute FK_Data_X fixups to relocs

Alex Bradbury via llvm-commits llvm-commits at lists.llvm.org
Mon Aug 19 06:23:03 PDT 2019


Author: asb
Date: Mon Aug 19 06:23:02 2019
New Revision: 369257

URL: http://llvm.org/viewvc/llvm-project?rev=369257&view=rev
Log:
[RISCV] Don't force absolute FK_Data_X fixups to relocs

The current behavior of shouldForceRelocation forces relocations for the
majority of fixups when relaxation is enabled. This makes sense for
fixups which incorporate symbols but is unnecessary for simple data
fixups where the fixup target is already resolved to an absolute value.

Differential Revision: https://reviews.llvm.org/D63404
Patch by Edward Jones.

Modified:
    llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
    llvm/trunk/test/MC/RISCV/fde-reloc.s
    llvm/trunk/test/MC/RISCV/linker-relaxation.s

Modified: llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp?rev=369257&r1=369256&r2=369257&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp Mon Aug 19 06:23:02 2019
@@ -33,6 +33,13 @@ bool RISCVAsmBackend::shouldForceRelocat
   switch ((unsigned)Fixup.getKind()) {
   default:
     break;
+  case FK_Data_1:
+  case FK_Data_2:
+  case FK_Data_4:
+  case FK_Data_8:
+    if (Target.isAbsolute())
+      return false;
+    break;
   case RISCV::fixup_riscv_got_hi20:
   case RISCV::fixup_riscv_tls_got_hi20:
   case RISCV::fixup_riscv_tls_gd_hi20:

Modified: llvm/trunk/test/MC/RISCV/fde-reloc.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/RISCV/fde-reloc.s?rev=369257&r1=369256&r2=369257&view=diff
==============================================================================
--- llvm/trunk/test/MC/RISCV/fde-reloc.s (original)
+++ llvm/trunk/test/MC/RISCV/fde-reloc.s Mon Aug 19 06:23:02 2019
@@ -14,9 +14,6 @@ func:
 # preparation for follow-on patches to fix it.
 
 # RELAX-RELOC:   Section (4) .rela.eh_frame {
-# RELAX-RELOC-NEXT:   0x0 R_RISCV_32 - 0x10
-# RELAX-RELOC-NEXT:   0x14 R_RISCV_32 - 0x10
-# RELAX-RELOC-NEXT:   0x18 R_RISCV_32 - 0x18
 # RELAX-RELOC-NEXT:   0x1C R_RISCV_ADD32 - 0x0
 # RELAX-RELOC-NEXT:   0x1C R_RISCV_SUB32 - 0x0
 # RELAX-RELOC-NEXT:   0x20 R_RISCV_ADD32 - 0x0

Modified: llvm/trunk/test/MC/RISCV/linker-relaxation.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/RISCV/linker-relaxation.s?rev=369257&r1=369256&r2=369257&view=diff
==============================================================================
--- llvm/trunk/test/MC/RISCV/linker-relaxation.s (original)
+++ llvm/trunk/test/MC/RISCV/linker-relaxation.s Mon Aug 19 06:23:02 2019
@@ -136,3 +136,24 @@ sb t1, %pcrel_lo(2b)(a2)
 # RELAX-RELOC: R_RISCV_RELAX - 0x0
 # RELAX-FIXUP: fixup A - offset: 0, value: %pcrel_lo(.Ltmp1), kind: fixup_riscv_pcrel_lo12_s
 # RELAX-FIXUP: fixup B - offset: 0, value: 0, kind: fixup_riscv_relax
+
+# Check that a relocation is not emitted for a symbol difference which has
+# been folded to a fixup with an absolute value. This can happen when a
+# difference expression refers to two symbols, at least one of which is
+# not defined at the point it is referenced. Then during *assembler*
+# relaxation when both symbols have become defined the difference may be folded
+# down to a fixup simply containing the absolute value. We want to ensure that
+# we don't force a relocation to be emitted for this absolute value even
+# when linker relaxation is enabled. The reason for this is that one instance
+# where this pattern appears in in the .eh_frame section (the CIE 'length'
+# field), and the .eh_frame section cannot be parsed by the linker unless the
+# fixup has been resolved to a concrete value instead of a relocation.
+  .data
+lo:
+  .word hi-lo
+  .quad hi-lo
+# NORELAX-RELOC-NOT: R_RISCV_32
+# NORELAX-RELOC-NOT: R_RISCV_64
+# RELAX-RELOC-NOT: R_RISCV_32
+# RELAX-RELOC-NOT: R_RISCV_64
+hi:




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