[llvm] r369228 - [X86] Fix the lower1BitShuffle code added in r369215 to correctly pass the widened vector to the KSHIFT node.

[Craig Topper via llvm-commits]

Author: ctopper
Date: Sun Aug 18 21:08:44 2019
New Revision: 369228

URL: http://llvm.org/viewvc/llvm-project?rev=369228&view=rev
Log:
[X86] Fix the lower1BitShuffle code added in r369215 to correctly pass the widened vector to the KSHIFT node.

Not sure how to test this as we have tests that exercise this code,
but nothing failed for the types not matching. Since all the k-registers
use equivalent register classes everything just ends up working.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=369228&r1=369227&r2=369228&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sun Aug 18 21:08:44 2019
@@ -16654,7 +16654,7 @@ static SDValue lower1BitShuffle(const SD
         SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, WideVT,
                                   DAG.getUNDEF(WideVT), V,
                                   DAG.getIntPtrConstant(0, DL));
-        Res = DAG.getNode(Opcode, DL, WideVT, V,
+        Res = DAG.getNode(Opcode, DL, WideVT, Res,
                           DAG.getConstant(ShiftAmt, DL, MVT::i8));
         return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, Res,
                            DAG.getIntPtrConstant(0, DL));