[PATCH] D66252: [RISCV] Convert registers from unsigned to Register

[Luís Marques via Phabricator via llvm-commits]

luismarques updated this revision to Diff 215371.
luismarques added a comment.

Convert `RISCVOperand::KindTy` from an enum to an enum class, to avoid collisions with `Register`.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D66252/new/

https://reviews.llvm.org/D66252

Files:
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
  llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
  llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
  llvm/lib/Target/RISCV/RISCVFrameLowering.h
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.h
  llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp

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