[PATCH] D66243: [ARM][LowOverheadLoops] Fix generated code for "revert".

[Eli Friedman via Phabricator via llvm-commits]

efriedma created this revision.
efriedma added reviewers: samparker, dmgreen, SjoerdMeijer.
Herald added subscribers: kristof.beyls, javed.absar.
Herald added a project: LLVM.

Two issues:

1. t2CMPri shouldn't use CPSR if it isn't predicated. This doesn't really have any visible effect at the moment, but it might matter in the future.
2. The t2CMPri generated for t2WhileLoopStart might need to use a register that isn't LR.

My team found this because we have a patch to track register liveness late in the pass pipeline.  I'll look into upstreaming it to help catch issues like this earlier.


Repository:
  rL LLVM

https://reviews.llvm.org/D66243

Files:
  lib/Target/ARM/ARMLowOverheadLoops.cpp
  test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir
  test/CodeGen/Thumb2/LowOverheadLoops/revert-non-loop.mir
  test/CodeGen/Thumb2/LowOverheadLoops/revert-while.mir


Index: test/CodeGen/Thumb2/LowOverheadLoops/revert-while.mir
===================================================================
--- test/CodeGen/Thumb2/LowOverheadLoops/revert-while.mir
+++ test/CodeGen/Thumb2/LowOverheadLoops/revert-while.mir
@@ -1,14 +1,14 @@
 # RUN: llc -mtriple=thumbv8.1m.main -mattr=+lob -run-pass=arm-low-overhead-loops --verify-machineinstrs %s -o - | FileCheck %s
 # CHECK:      body:
 # CHECK:      bb.0.entry:
-# CHECK:        t2CMPri $lr, 0, 14
+# CHECK:        t2CMPri $r3, 0, 14
 # CHECK-NEXT:   t2Bcc %bb.3, 0, $cpsr
 # CHECK-NEXT:   tB %bb.1
 # CHECK:      bb.1.do.body.preheader:
 # CHECK:        $lr = tMOVr killed $r3
 # CHECK:      bb.2.do.body:
 # CHECK:        $lr = t2SUBri killed renamable $lr, 1, 14
-# CHECK-NEXT:   t2CMPri $lr, 0, 14, $cpsr
+# CHECK-NEXT:   t2CMPri $lr, 0, 14, $noreg, implicit-def $cpsr
 # CHECK-NEXT:   t2Bcc %bb.2, 1, $cpsr
 # CHECK-NEXT:   tB %bb.3, 14
 
Index: test/CodeGen/Thumb2/LowOverheadLoops/revert-non-loop.mir
===================================================================
--- test/CodeGen/Thumb2/LowOverheadLoops/revert-non-loop.mir
+++ test/CodeGen/Thumb2/LowOverheadLoops/revert-non-loop.mir
@@ -4,7 +4,7 @@
 # CHECK: bb.0.entry:
 # CHECK:   tBcc %bb.2, 3
 # CHECK: bb.1.not.preheader:
-# CHECK:   t2CMPri $lr, 0, 14
+# CHECK:   t2CMPri renamable $lr, 0, 14
 # CHECK:   t2Bcc %bb.4, 0
 # CHECK:   tB %bb.2
 # CHECK: bb.3.while.body:
Index: test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir
===================================================================
--- test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir
+++ test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir
@@ -3,7 +3,7 @@
 # CHECK-NOT: DoLoopStart
 # CHECK-NOT: DLS
 # CHECK: bb.1.for.body:
-# CHECK:   t2CMPri $lr, 0, 14, $cpsr, implicit-def $cpsr
+# CHECK:   t2CMPri $lr, 0, 14, $noreg, implicit-def $cpsr
 # CHECK:   t2Bcc %bb.3, 1, $cpsr
 # CHECK:   tB %bb.2, 14, $noreg
 # CHECK: bb.2.for.cond.cleanup:
Index: lib/Target/ARM/ARMLowOverheadLoops.cpp
===================================================================
--- lib/Target/ARM/ARMLowOverheadLoops.cpp
+++ lib/Target/ARM/ARMLowOverheadLoops.cpp
@@ -251,10 +251,10 @@
   MachineBasicBlock *MBB = MI->getParent();
   MachineInstrBuilder MIB = BuildMI(*MBB, MI, MI->getDebugLoc(),
                                     TII->get(ARM::t2CMPri));
-  MIB.addReg(ARM::LR);
+  MIB.add(MI->getOperand(0));
   MIB.addImm(0);
   MIB.addImm(ARMCC::AL);
-  MIB.addReg(ARM::CPSR);
+  MIB.addReg(ARM::NoRegister);
 
   // TODO: Try to use tBcc instead
   MIB = BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(ARM::t2Bcc));
@@ -292,7 +292,7 @@
   MIB.addReg(ARM::LR);
   MIB.addImm(0);
   MIB.addImm(ARMCC::AL);
-  MIB.addReg(ARM::CPSR);
+  MIB.addReg(ARM::NoRegister);
 
   // TODO Try to use tBcc instead.
   // Create bne


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