[PATCH] D66236: [SDAG][x86] check for relaxed math when matching an FP reduction

[Sanjay Patel via Phabricator via llvm-commits]

spatel created this revision.
spatel added reviewers: RKSimon, craig.topper, xbolva00.
Herald added subscribers: hiraditya, mcrosier.
Herald added a project: LLVM.

If the last step in a reduction allows reassociation and doesn't care about -0.0, then we are free to recognize that computation as a reduction that may reorder the intermediate steps.

This is requested directly by PR42705:
https://bugs.llvm.org/show_bug.cgi?id=42705
and solves PR42947 (if horizontal math instructions are actually faster than the alternative):
https://bugs.llvm.org/show_bug.cgi?id=42947


https://reviews.llvm.org/D66236

Files:
  llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/test/CodeGen/X86/haddsub.ll
  llvm/test/CodeGen/X86/vector-reduce-fadd-fast.ll

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