[PATCH] D66163: [AArch64][GlobalISel] Select patterns which use shifted register operands

[Amara Emerson via Phabricator via llvm-commits]

aemerson added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp:4553
+  unsigned NumBits =
+      MRI.getType(ShiftInst->getOperand(0).getReg()).getSizeInBits();
+  unsigned Val = *Immed & (NumBits - 1);
----------------
Can simplify this a bit to `MRI.getType(ShiftReg).getSizeInBits();`


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Comment at: llvm/test/CodeGen/AArch64/GlobalISel/select-arith-shifted-reg.mir:37
+    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+    ; CHECK: [[ADDXrs:%[0-9]+]]:gpr64 = ADDXrs [[COPY]], [[COPY]], 8
+    ; CHECK: $x0 = COPY [[ADDXrs]]
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The checks here are identical to the rhs case. Should we be trying to test a less degenerate case? Like:
    %0:gpr(s64) = COPY $x0
    %param2:gpr(s64) = COPY $x1
    %1:gpr(s64) = G_CONSTANT i64 8
    %2:gpr(s64) = G_SHL %0, %1:gpr(s64)
    %3:gpr(s64) = G_ADD %2, %param2:gpr(s64)


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D66163/new/

https://reviews.llvm.org/D66163