[PATCH] D66095: [InstCombine] canonicalize a scalar-select-of-vectors to vector select

Roman Lebedev via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Aug 13 10:21:59 PDT 2019


lebedev.ri added a comment.

The codegen improvement is a bug in `X86TargetLowering::LowerSELECT()`, not dis-similar to https://bugs.llvm.org/show_bug.cgi?id=42903
It never even tries to lower integer vector select to blend, but produces `cmov`

  Optimized type-legalized selection DAG: %bb.0 'extract_cond:'
  SelectionDAG has 17 nodes:
    t0: ch = EntryToken
              t6: v4i32,ch = CopyFromReg t0, Register:v4i32 %2
            t21: v16i8 = bitcast t6
          t23: i8 = extract_vector_elt t21, Constant:i64<12>
        t20: i8 = and t23, Constant:i8<1>
        t2: v4i32,ch = CopyFromReg t0, Register:v4i32 %0
        t4: v4i32,ch = CopyFromReg t0, Register:v4i32 %1
      t11: v4i32 = select t20, t2, t4
    t14: ch,glue = CopyToReg t0, Register:v4i32 $xmm0, t11
    t15: ch = X86ISD::RET_FLAG t14, TargetConstant:i32<0>, Register:v4i32 $xmm0, t14:1
  
  
  
  Legalizing vector op: t11: v4i32 = select t20, t2, t4
  Trying custom legalization
  Creating constant: t24: i8 = Constant<5>
  Creating constant: t25: i8 = Constant<0>
  Creating new node: t26: i32 = X86ISD::CMP t20, Constant:i8<0>
  Creating new node: t27: v4i32 = X86ISD::CMOV t4, t2, Constant:i8<5>, t26
  Successfully custom legalized node
  Vector-legalized selection DAG: %bb.0 'extract_cond:'
  SelectionDAG has 20 nodes:
    t0: ch = EntryToken
        t4: v4i32,ch = CopyFromReg t0, Register:v4i32 %1
        t2: v4i32,ch = CopyFromReg t0, Register:v4i32 %0
                t6: v4i32,ch = CopyFromReg t0, Register:v4i32 %2
              t21: v16i8 = bitcast t6
            t23: i8 = extract_vector_elt t21, Constant:i64<12>
          t20: i8 = and t23, Constant:i8<1>
        t26: i32 = X86ISD::CMP t20, Constant:i8<0>
      t27: v4i32 = X86ISD::CMOV t4, t2, Constant:i8<5>, t26
    t14: ch,glue = CopyToReg t0, Register:v4i32 $xmm0, t27
    t15: ch = X86ISD::RET_FLAG t14, TargetConstant:i32<0>, Register:v4i32 $xmm0, t14:1

I'm honestly not sure here if i would consider splat-of-i1 or i1 more canonical,
i would kind-of guessed i1 since it is a single bit while vector isn't.


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  https://reviews.llvm.org/D66095/new/

https://reviews.llvm.org/D66095





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