[llvm] r368557 - [X86][SSE] Add test showing missing compute known bits PSADBW handling

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Mon Aug 12 05:13:08 2019
New Revision: 368557

URL: http://llvm.org/viewvc/llvm-project?rev=368557&view=rev
Log:
[X86][SSE] Add test showing missing compute known bits PSADBW handling

The upper 48-bits of each i64 element is guaranteed to be zero.

Added:
    llvm/trunk/test/CodeGen/X86/psadbw.ll

Added: llvm/trunk/test/CodeGen/X86/psadbw.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/psadbw.ll?rev=368557&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/psadbw.ll (added)
+++ llvm/trunk/test/CodeGen/X86/psadbw.ll Mon Aug 12 05:13:08 2019
@@ -0,0 +1,18 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,X86
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,X64
+
+; Only bottom 16 bits are set - upper 48 bits are zero.
+define <2 x i64> @combine_psadbw_shift(<16 x i8> %0, <16 x i8> %1) {
+; CHECK-LABEL: combine_psadbw_shift:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    psadbw %xmm1, %xmm0
+; CHECK-NEXT:    psrlq $48, %xmm0
+; CHECK-NEXT:    ret{{[l|q]}}
+  %3 = tail call <2 x i64> @llvm.x86.sse2.psad.bw(<16 x i8> %0, <16 x i8> %1)
+  %4 = lshr <2 x i64> %3, <i64 48, i64 48>
+  ret <2 x i64> %4
+}
+
+declare <2 x i64> @llvm.x86.sse2.psad.bw(<16 x i8>, <16 x i8>)
+