[PATCH] D64425: [RISCV] Fix ICE in isDesirableToCommuteWithShift

[Sam Elliott via Phabricator via llvm-commits]

lenary marked an inline comment as done.
lenary added inline comments.


================
Comment at: llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp:1010
       // later.
       if (isLegalAddImmediate(ShiftedC1Int.getSExtValue()))
         return true;
----------------
apazos wrote:
> Sam, I just noted when building compiler-rt (/compiler-rt/lib/builtins/addtf3.c) in debug mode, it crashes in this line.
> 
> The reason is ShiftedC1Int bitwidth is 128, but APInt getSExtValue expects a 64 bit quantity.
> 
> Can you take a look?
> 
> One solution is:
> 
> --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
> +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
> @@ -1003,6 +1003,8 @@ bool RISCVTargetLowering::isDesirableToCommuteWithShift(
>      if (C1 && C2) {
>        APInt C1Int = C1->getAPIntValue();
>        APInt ShiftedC1Int = C1Int << C2->getAPIntValue();
> +      if (ShiftedC1Int.getBitWidth() > 64)
> +        return false;
> 
> Reduced test case:
> 
> define void @test(i128* %a) {
> entry:
>   %load = load i128, i128* %a, align 16
>   %or = or i128 %load, 5192296858534827628530496329220096
>   %shl = shl i128 %or, 3
>   store i128 %shl, i128* %a, align 16
>  ret void
> }
> 
> 
Thanks for letting me know. I have prepared a patch for this, including a variant of your testcase (which I have verified currently causes the same ICE you're seeing). It is D66081


Repository:
  rL LLVM

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  https://reviews.llvm.org/D64425/new/

https://reviews.llvm.org/D64425