[PATCH] D66069: [X86] Use PSADBW for v8i8 addition reductions.

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


================
Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:35451
+    Rdx = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, Rdx,
+                      DAG.getUNDEF(VecVT));
+    Rdx = DAG.getNode(X86ISD::PSADBW, DL, MVT::v2i64, Rdx,
----------------
we can easily support 2i8/4i8 as well by replacing this with an insertion into a zero v16i8 vector


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  https://reviews.llvm.org/D66069/new/

https://reviews.llvm.org/D66069