[PATCH] D65966: AMDGPU/SILoadStoreOptimizer: Improve merging of out of order offsets

[Tom Stellard via Phabricator via llvm-commits]

tstellar created this revision.
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This improves merging of sequences like:

store a, ptr + 4
store b, ptr + 8
store c, ptr + 12
store d, ptr + 16
store e, ptr + 20
store f, ptr

Prior to this patch the basic block was scanned in order to find instructions
to merge and the above sequence would be transformed to:

store4 <a, b, c, d>, ptr + 4
store e, ptr + 20
store r, ptr

With this change, we now sort all the candidate merge instructions by their offset,
so instructions are visited in offset order rather than in the order they appear
in the basic block.  We now transform this sequnce into:

store4 <f, a, b, c>, ptr
store2 <d, e>, ptr + 16

Another benefit of this change is that since we have sorted the mergeable lists
by offset, we can easily check if an instruction is mergeable by checking the
offset of the instruction that becomes before or after it in the sorted list.
Once we determine an instruction is not mergeable we can remove it from the list
and avoid having to do the more expensive mergeablilty checks.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D65966

Files:
  llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
  llvm/test/CodeGen/AMDGPU/ds_read2_offset_order.ll
  llvm/test/CodeGen/AMDGPU/merge-load-store.mir

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