[llvm] r368274 - [MIPS GlobalISel] Select jump_table and brjt
Petar Avramovic via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 8 03:21:12 PDT 2019
Author: petar.avramovic
Date: Thu Aug 8 03:21:12 2019
New Revision: 368274
URL: http://llvm.org/viewvc/llvm-project?rev=368274&view=rev
Log:
[MIPS GlobalISel] Select jump_table and brjt
G_JUMP_TABLE and G_BRJT appear from translation of switch statement.
Select these two instructions for MIPS32, both pic and non-pic.
Differential Revision: https://reviews.llvm.org/D65861
Added:
llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/jump_table_and_brjt.mir
llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/jump_table_and_brjt.mir
llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/jump_table_and_brjt.ll
llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/jump_table_and_brjt.mir
Modified:
llvm/trunk/lib/Target/Mips/MipsInstructionSelector.cpp
llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp
llvm/trunk/lib/Target/Mips/MipsRegisterBankInfo.cpp
Modified: llvm/trunk/lib/Target/Mips/MipsInstructionSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstructionSelector.cpp?rev=368274&r1=368273&r2=368274&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstructionSelector.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstructionSelector.cpp Thu Aug 8 03:21:12 2019
@@ -17,6 +17,7 @@
#include "MipsTargetMachine.h"
#include "llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h"
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
+#include "llvm/CodeGen/MachineJumpTableInfo.h"
#define DEBUG_TYPE "mips-isel"
@@ -284,6 +285,60 @@ bool MipsInstructionSelector::select(Mac
.add(I.getOperand(1));
break;
}
+ case G_BRJT: {
+ unsigned EntrySize =
+ MF.getJumpTableInfo()->getEntrySize(MF.getDataLayout());
+ assert(isPowerOf2_32(EntrySize) &&
+ "Non-power-of-two jump-table entry size not supported.");
+
+ Register JTIndex = MRI.createVirtualRegister(&Mips::GPR32RegClass);
+ MachineInstr *SLL = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::SLL))
+ .addDef(JTIndex)
+ .addUse(I.getOperand(2).getReg())
+ .addImm(Log2_32(EntrySize));
+ if (!constrainSelectedInstRegOperands(*SLL, TII, TRI, RBI))
+ return false;
+
+ Register DestAddress = MRI.createVirtualRegister(&Mips::GPR32RegClass);
+ MachineInstr *ADDu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu))
+ .addDef(DestAddress)
+ .addUse(I.getOperand(0).getReg())
+ .addUse(JTIndex);
+ if (!constrainSelectedInstRegOperands(*ADDu, TII, TRI, RBI))
+ return false;
+
+ Register Dest = MRI.createVirtualRegister(&Mips::GPR32RegClass);
+ MachineInstr *LW =
+ BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW))
+ .addDef(Dest)
+ .addUse(DestAddress)
+ .addJumpTableIndex(I.getOperand(1).getIndex(), MipsII::MO_ABS_LO)
+ .addMemOperand(MF.getMachineMemOperand(
+ MachinePointerInfo(), MachineMemOperand::MOLoad, 4, 4));
+ if (!constrainSelectedInstRegOperands(*LW, TII, TRI, RBI))
+ return false;
+
+ if (MF.getTarget().isPositionIndependent()) {
+ Register DestTmp = MRI.createVirtualRegister(&Mips::GPR32RegClass);
+ LW->getOperand(0).setReg(DestTmp);
+ MachineInstr *ADDu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu))
+ .addDef(Dest)
+ .addUse(DestTmp)
+ .addUse(MF.getInfo<MipsFunctionInfo>()
+ ->getGlobalBaseRegForGlobalISel());
+ if (!constrainSelectedInstRegOperands(*ADDu, TII, TRI, RBI))
+ return false;
+ }
+
+ MachineInstr *Branch =
+ BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoIndirectBranch))
+ .addUse(Dest);
+ if (!constrainSelectedInstRegOperands(*Branch, TII, TRI, RBI))
+ return false;
+
+ I.eraseFromParent();
+ return true;
+ }
case G_PHI: {
const Register DestReg = I.getOperand(0).getReg();
const unsigned OpSize = MRI.getType(DestReg).getSizeInBits();
@@ -522,6 +577,24 @@ bool MipsInstructionSelector::select(Mac
I.eraseFromParent();
return true;
}
+ case G_JUMP_TABLE: {
+ if (MF.getTarget().isPositionIndependent()) {
+ MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW))
+ .addDef(I.getOperand(0).getReg())
+ .addReg(MF.getInfo<MipsFunctionInfo>()
+ ->getGlobalBaseRegForGlobalISel())
+ .addJumpTableIndex(I.getOperand(1).getIndex(), MipsII::MO_GOT)
+ .addMemOperand(
+ MF.getMachineMemOperand(MachinePointerInfo::getGOT(MF),
+ MachineMemOperand::MOLoad, 4, 4));
+ } else {
+ MI =
+ BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LUi))
+ .addDef(I.getOperand(0).getReg())
+ .addJumpTableIndex(I.getOperand(1).getIndex(), MipsII::MO_ABS_HI);
+ }
+ break;
+ }
case G_ICMP: {
struct Instr {
unsigned Opcode;
Modified: llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp?rev=368274&r1=368273&r2=368274&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsLegalizerInfo.cpp Thu Aug 8 03:21:12 2019
@@ -63,6 +63,9 @@ MipsLegalizerInfo::MipsLegalizerInfo(con
.legalFor({s32})
.minScalar(0, s32);
+ getActionDefinitionsBuilder(G_BRJT)
+ .legalFor({{p0, s32}});
+
getActionDefinitionsBuilder(G_PHI)
.legalFor({p0, s32, s64})
.minScalar(0, s32);
@@ -98,7 +101,7 @@ MipsLegalizerInfo::MipsLegalizerInfo(con
getActionDefinitionsBuilder(G_FRAME_INDEX)
.legalFor({p0});
- getActionDefinitionsBuilder(G_GLOBAL_VALUE)
+ getActionDefinitionsBuilder({G_GLOBAL_VALUE, G_JUMP_TABLE})
.legalFor({p0});
// FP instructions
Modified: llvm/trunk/lib/Target/Mips/MipsRegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterBankInfo.cpp?rev=368274&r1=368273&r2=368274&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsRegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsRegisterBankInfo.cpp Thu Aug 8 03:21:12 2019
@@ -576,10 +576,16 @@ MipsRegisterBankInfo::getInstrMapping(co
case G_CONSTANT:
case G_FRAME_INDEX:
case G_GLOBAL_VALUE:
+ case G_JUMP_TABLE:
case G_BRCOND:
OperandsMapping =
getOperandsMapping({&Mips::ValueMappings[Mips::GPRIdx], nullptr});
break;
+ case G_BRJT:
+ OperandsMapping =
+ getOperandsMapping({&Mips::ValueMappings[Mips::GPRIdx], nullptr,
+ &Mips::ValueMappings[Mips::GPRIdx]});
+ break;
case G_ICMP:
OperandsMapping =
getOperandsMapping({&Mips::ValueMappings[Mips::GPRIdx], nullptr,
Added: llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/jump_table_and_brjt.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/jump_table_and_brjt.mir?rev=368274&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/jump_table_and_brjt.mir (added)
+++ llvm/trunk/test/CodeGen/Mips/GlobalISel/instruction-select/jump_table_and_brjt.mir Thu Aug 8 03:21:12 2019
@@ -0,0 +1,291 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -relocation-model=pic -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32_PIC
+--- |
+
+ define i32 @mod4_0_to_11(i32 %a) {
+ entry:
+ switch i32 %a, label %sw.default [
+ i32 0, label %sw.bb
+ i32 4, label %sw.bb
+ i32 1, label %sw.bb1
+ i32 5, label %sw.bb1
+ i32 2, label %sw.bb2
+ i32 6, label %sw.bb2
+ i32 3, label %sw.bb3
+ i32 7, label %sw.bb3
+ ]
+
+ sw.bb: ; preds = %entry, %entry
+ ret i32 0
+
+ sw.bb1: ; preds = %entry, %entry
+ ret i32 1
+
+ sw.bb2: ; preds = %entry, %entry
+ ret i32 2
+
+ sw.bb3: ; preds = %entry, %entry
+ ret i32 3
+
+ sw.default: ; preds = %entry
+ br label %sw.epilog
+
+ sw.epilog: ; preds = %sw.default
+ switch i32 %a, label %sw.default8 [
+ i32 8, label %sw.bb4
+ i32 9, label %sw.bb5
+ i32 10, label %sw.bb6
+ i32 11, label %sw.bb7
+ ]
+
+ sw.bb4: ; preds = %sw.epilog
+ ret i32 0
+
+ sw.bb5: ; preds = %sw.epilog
+ ret i32 1
+
+ sw.bb6: ; preds = %sw.epilog
+ ret i32 2
+
+ sw.bb7: ; preds = %sw.epilog
+ ret i32 3
+
+ sw.default8: ; preds = %sw.epilog
+ ret i32 -1
+ }
+
+...
+---
+name: mod4_0_to_11
+alignment: 2
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+jumpTable:
+ kind: block-address
+ entries:
+ - id: 0
+ blocks: [ '%bb.2', '%bb.3', '%bb.4', '%bb.5', '%bb.2', '%bb.3',
+ '%bb.4', '%bb.5' ]
+ - id: 1
+ blocks: [ '%bb.8', '%bb.9', '%bb.10', '%bb.11' ]
+body: |
+ ; MIPS32-LABEL: name: mod4_0_to_11
+ ; MIPS32: bb.0.entry:
+ ; MIPS32: successors: %bb.6(0x40000000), %bb.1(0x40000000)
+ ; MIPS32: liveins: $a0
+ ; MIPS32: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+ ; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 7
+ ; MIPS32: [[ORi1:%[0-9]+]]:gpr32 = ORi $zero, 3
+ ; MIPS32: [[ORi2:%[0-9]+]]:gpr32 = ORi $zero, 2
+ ; MIPS32: [[ORi3:%[0-9]+]]:gpr32 = ORi $zero, 1
+ ; MIPS32: [[ORi4:%[0-9]+]]:gpr32 = ORi $zero, 0
+ ; MIPS32: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 65535
+ ; MIPS32: [[ORi5:%[0-9]+]]:gpr32 = ORi $zero, 0
+ ; MIPS32: [[SUBu:%[0-9]+]]:gpr32 = SUBu [[COPY]], [[ORi5]]
+ ; MIPS32: [[SLTu:%[0-9]+]]:gpr32 = SLTu [[ORi]], [[SUBu]]
+ ; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[SLTu]], [[ORi3]]
+ ; MIPS32: BNE [[AND]], $zero, %bb.6, implicit-def $at
+ ; MIPS32: bb.1.entry:
+ ; MIPS32: successors: %bb.2(0x20000000), %bb.3(0x20000000), %bb.4(0x20000000), %bb.5(0x20000000)
+ ; MIPS32: [[LUi:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) %jump-table.0
+ ; MIPS32: [[SLL:%[0-9]+]]:gpr32 = SLL [[SUBu]], 2
+ ; MIPS32: [[ADDu:%[0-9]+]]:gpr32 = ADDu [[LUi]], [[SLL]]
+ ; MIPS32: [[LW:%[0-9]+]]:gpr32 = LW [[ADDu]], target-flags(mips-abs-lo) %jump-table.0 :: (load 4)
+ ; MIPS32: PseudoIndirectBranch [[LW]]
+ ; MIPS32: bb.2.sw.bb:
+ ; MIPS32: $v0 = COPY [[ORi4]]
+ ; MIPS32: RetRA implicit $v0
+ ; MIPS32: bb.3.sw.bb1:
+ ; MIPS32: $v0 = COPY [[ORi3]]
+ ; MIPS32: RetRA implicit $v0
+ ; MIPS32: bb.4.sw.bb2:
+ ; MIPS32: $v0 = COPY [[ORi2]]
+ ; MIPS32: RetRA implicit $v0
+ ; MIPS32: bb.5.sw.bb3:
+ ; MIPS32: $v0 = COPY [[ORi1]]
+ ; MIPS32: RetRA implicit $v0
+ ; MIPS32: bb.6.sw.default:
+ ; MIPS32: successors: %bb.7(0x80000000)
+ ; MIPS32: bb.7.sw.epilog:
+ ; MIPS32: successors: %bb.13(0x40000000), %bb.8(0x40000000)
+ ; MIPS32: [[ORi6:%[0-9]+]]:gpr32 = ORi $zero, 8
+ ; MIPS32: [[SUBu1:%[0-9]+]]:gpr32 = SUBu [[COPY]], [[ORi6]]
+ ; MIPS32: [[SLTu1:%[0-9]+]]:gpr32 = SLTu [[ORi1]], [[SUBu1]]
+ ; MIPS32: [[ORi7:%[0-9]+]]:gpr32 = ORi $zero, 1
+ ; MIPS32: [[AND1:%[0-9]+]]:gpr32 = AND [[SLTu1]], [[ORi7]]
+ ; MIPS32: BNE [[AND1]], $zero, %bb.13, implicit-def $at
+ ; MIPS32: bb.8.sw.epilog:
+ ; MIPS32: successors: %bb.9(0x20000000), %bb.10(0x20000000), %bb.11(0x20000000), %bb.12(0x20000000)
+ ; MIPS32: [[LUi1:%[0-9]+]]:gpr32 = LUi target-flags(mips-abs-hi) %jump-table.1
+ ; MIPS32: [[SLL1:%[0-9]+]]:gpr32 = SLL [[SUBu1]], 2
+ ; MIPS32: [[ADDu1:%[0-9]+]]:gpr32 = ADDu [[LUi1]], [[SLL1]]
+ ; MIPS32: [[LW1:%[0-9]+]]:gpr32 = LW [[ADDu1]], target-flags(mips-abs-lo) %jump-table.1 :: (load 4)
+ ; MIPS32: PseudoIndirectBranch [[LW1]]
+ ; MIPS32: bb.9.sw.bb4:
+ ; MIPS32: $v0 = COPY [[ORi4]]
+ ; MIPS32: RetRA implicit $v0
+ ; MIPS32: bb.10.sw.bb5:
+ ; MIPS32: $v0 = COPY [[ORi3]]
+ ; MIPS32: RetRA implicit $v0
+ ; MIPS32: bb.11.sw.bb6:
+ ; MIPS32: $v0 = COPY [[ORi2]]
+ ; MIPS32: RetRA implicit $v0
+ ; MIPS32: bb.12.sw.bb7:
+ ; MIPS32: $v0 = COPY [[ORi1]]
+ ; MIPS32: RetRA implicit $v0
+ ; MIPS32: bb.13.sw.default8:
+ ; MIPS32: $v0 = COPY [[ADDiu]]
+ ; MIPS32: RetRA implicit $v0
+ ; MIPS32_PIC-LABEL: name: mod4_0_to_11
+ ; MIPS32_PIC: bb.0.entry:
+ ; MIPS32_PIC: successors: %bb.6(0x40000000), %bb.1(0x40000000)
+ ; MIPS32_PIC: liveins: $a0, $t9, $v0
+ ; MIPS32_PIC: [[ADDu:%[0-9]+]]:gpr32 = ADDu $v0, $t9
+ ; MIPS32_PIC: [[COPY:%[0-9]+]]:gpr32 = COPY $a0
+ ; MIPS32_PIC: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 7
+ ; MIPS32_PIC: [[ORi1:%[0-9]+]]:gpr32 = ORi $zero, 3
+ ; MIPS32_PIC: [[ORi2:%[0-9]+]]:gpr32 = ORi $zero, 2
+ ; MIPS32_PIC: [[ORi3:%[0-9]+]]:gpr32 = ORi $zero, 1
+ ; MIPS32_PIC: [[ORi4:%[0-9]+]]:gpr32 = ORi $zero, 0
+ ; MIPS32_PIC: [[ADDiu:%[0-9]+]]:gpr32 = ADDiu $zero, 65535
+ ; MIPS32_PIC: [[ORi5:%[0-9]+]]:gpr32 = ORi $zero, 0
+ ; MIPS32_PIC: [[SUBu:%[0-9]+]]:gpr32 = SUBu [[COPY]], [[ORi5]]
+ ; MIPS32_PIC: [[SLTu:%[0-9]+]]:gpr32 = SLTu [[ORi]], [[SUBu]]
+ ; MIPS32_PIC: [[AND:%[0-9]+]]:gpr32 = AND [[SLTu]], [[ORi3]]
+ ; MIPS32_PIC: BNE [[AND]], $zero, %bb.6, implicit-def $at
+ ; MIPS32_PIC: bb.1.entry:
+ ; MIPS32_PIC: successors: %bb.2(0x20000000), %bb.3(0x20000000), %bb.4(0x20000000), %bb.5(0x20000000)
+ ; MIPS32_PIC: [[LW:%[0-9]+]]:gpr32 = LW [[ADDu]], target-flags(mips-got) %jump-table.0 :: (load 4 from got)
+ ; MIPS32_PIC: [[SLL:%[0-9]+]]:gpr32 = SLL [[SUBu]], 2
+ ; MIPS32_PIC: [[ADDu1:%[0-9]+]]:gpr32 = ADDu [[LW]], [[SLL]]
+ ; MIPS32_PIC: [[LW1:%[0-9]+]]:gpr32 = LW [[ADDu1]], target-flags(mips-abs-lo) %jump-table.0 :: (load 4)
+ ; MIPS32_PIC: [[ADDu2:%[0-9]+]]:gpr32 = ADDu [[LW1]], [[ADDu]]
+ ; MIPS32_PIC: PseudoIndirectBranch [[ADDu2]]
+ ; MIPS32_PIC: bb.2.sw.bb:
+ ; MIPS32_PIC: $v0 = COPY [[ORi4]]
+ ; MIPS32_PIC: RetRA implicit $v0
+ ; MIPS32_PIC: bb.3.sw.bb1:
+ ; MIPS32_PIC: $v0 = COPY [[ORi3]]
+ ; MIPS32_PIC: RetRA implicit $v0
+ ; MIPS32_PIC: bb.4.sw.bb2:
+ ; MIPS32_PIC: $v0 = COPY [[ORi2]]
+ ; MIPS32_PIC: RetRA implicit $v0
+ ; MIPS32_PIC: bb.5.sw.bb3:
+ ; MIPS32_PIC: $v0 = COPY [[ORi1]]
+ ; MIPS32_PIC: RetRA implicit $v0
+ ; MIPS32_PIC: bb.6.sw.default:
+ ; MIPS32_PIC: successors: %bb.7(0x80000000)
+ ; MIPS32_PIC: bb.7.sw.epilog:
+ ; MIPS32_PIC: successors: %bb.13(0x40000000), %bb.8(0x40000000)
+ ; MIPS32_PIC: [[ORi6:%[0-9]+]]:gpr32 = ORi $zero, 8
+ ; MIPS32_PIC: [[SUBu1:%[0-9]+]]:gpr32 = SUBu [[COPY]], [[ORi6]]
+ ; MIPS32_PIC: [[SLTu1:%[0-9]+]]:gpr32 = SLTu [[ORi1]], [[SUBu1]]
+ ; MIPS32_PIC: [[ORi7:%[0-9]+]]:gpr32 = ORi $zero, 1
+ ; MIPS32_PIC: [[AND1:%[0-9]+]]:gpr32 = AND [[SLTu1]], [[ORi7]]
+ ; MIPS32_PIC: BNE [[AND1]], $zero, %bb.13, implicit-def $at
+ ; MIPS32_PIC: bb.8.sw.epilog:
+ ; MIPS32_PIC: successors: %bb.9(0x20000000), %bb.10(0x20000000), %bb.11(0x20000000), %bb.12(0x20000000)
+ ; MIPS32_PIC: [[LW2:%[0-9]+]]:gpr32 = LW [[ADDu]], target-flags(mips-got) %jump-table.1 :: (load 4 from got)
+ ; MIPS32_PIC: [[SLL1:%[0-9]+]]:gpr32 = SLL [[SUBu1]], 2
+ ; MIPS32_PIC: [[ADDu3:%[0-9]+]]:gpr32 = ADDu [[LW2]], [[SLL1]]
+ ; MIPS32_PIC: [[LW3:%[0-9]+]]:gpr32 = LW [[ADDu3]], target-flags(mips-abs-lo) %jump-table.1 :: (load 4)
+ ; MIPS32_PIC: [[ADDu4:%[0-9]+]]:gpr32 = ADDu [[LW3]], [[ADDu]]
+ ; MIPS32_PIC: PseudoIndirectBranch [[ADDu4]]
+ ; MIPS32_PIC: bb.9.sw.bb4:
+ ; MIPS32_PIC: $v0 = COPY [[ORi4]]
+ ; MIPS32_PIC: RetRA implicit $v0
+ ; MIPS32_PIC: bb.10.sw.bb5:
+ ; MIPS32_PIC: $v0 = COPY [[ORi3]]
+ ; MIPS32_PIC: RetRA implicit $v0
+ ; MIPS32_PIC: bb.11.sw.bb6:
+ ; MIPS32_PIC: $v0 = COPY [[ORi2]]
+ ; MIPS32_PIC: RetRA implicit $v0
+ ; MIPS32_PIC: bb.12.sw.bb7:
+ ; MIPS32_PIC: $v0 = COPY [[ORi1]]
+ ; MIPS32_PIC: RetRA implicit $v0
+ ; MIPS32_PIC: bb.13.sw.default8:
+ ; MIPS32_PIC: $v0 = COPY [[ADDiu]]
+ ; MIPS32_PIC: RetRA implicit $v0
+ bb.1.entry:
+ liveins: $a0
+
+ %0:gprb(s32) = COPY $a0
+ %4:gprb(s32) = G_CONSTANT i32 7
+ %8:gprb(s32) = G_CONSTANT i32 3
+ %9:gprb(s32) = G_CONSTANT i32 2
+ %10:gprb(s32) = G_CONSTANT i32 1
+ %11:gprb(s32) = G_CONSTANT i32 0
+ %18:gprb(s32) = G_CONSTANT i32 -1
+ %1:gprb(s32) = G_CONSTANT i32 0
+ %2:gprb(s32) = G_SUB %0, %1
+ %3:gprb(s32) = COPY %2(s32)
+ %5:gprb(s32) = COPY %4(s32)
+ %22:gprb(s32) = G_ICMP intpred(ugt), %3(s32), %5
+ %23:gprb(s32) = COPY %22(s32)
+ %21:gprb(s32) = G_AND %23, %10
+ G_BRCOND %21(s32), %bb.6
+
+ bb.13.entry:
+ successors: %bb.2, %bb.3, %bb.4, %bb.5
+
+ %7:gprb(p0) = G_JUMP_TABLE %jump-table.0
+ G_BRJT %7(p0), %jump-table.0, %3(s32)
+
+ bb.2.sw.bb:
+ $v0 = COPY %11(s32)
+ RetRA implicit $v0
+
+ bb.3.sw.bb1:
+ $v0 = COPY %10(s32)
+ RetRA implicit $v0
+
+ bb.4.sw.bb2:
+ $v0 = COPY %9(s32)
+ RetRA implicit $v0
+
+ bb.5.sw.bb3:
+ $v0 = COPY %8(s32)
+ RetRA implicit $v0
+
+ bb.6.sw.default:
+
+ bb.7.sw.epilog:
+ %12:gprb(s32) = G_CONSTANT i32 8
+ %13:gprb(s32) = G_SUB %0, %12
+ %14:gprb(s32) = COPY %13(s32)
+ %15:gprb(s32) = COPY %8(s32)
+ %20:gprb(s32) = G_ICMP intpred(ugt), %14(s32), %15
+ %24:gprb(s32) = G_CONSTANT i32 1
+ %25:gprb(s32) = COPY %20(s32)
+ %19:gprb(s32) = G_AND %25, %24
+ G_BRCOND %19(s32), %bb.12
+
+ bb.14.sw.epilog:
+ successors: %bb.8, %bb.9, %bb.10, %bb.11
+
+ %17:gprb(p0) = G_JUMP_TABLE %jump-table.1
+ G_BRJT %17(p0), %jump-table.1, %14(s32)
+
+ bb.8.sw.bb4:
+ $v0 = COPY %11(s32)
+ RetRA implicit $v0
+
+ bb.9.sw.bb5:
+ $v0 = COPY %10(s32)
+ RetRA implicit $v0
+
+ bb.10.sw.bb6:
+ $v0 = COPY %9(s32)
+ RetRA implicit $v0
+
+ bb.11.sw.bb7:
+ $v0 = COPY %8(s32)
+ RetRA implicit $v0
+
+ bb.12.sw.default8:
+ $v0 = COPY %18(s32)
+ RetRA implicit $v0
+
+...
Added: llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/jump_table_and_brjt.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/jump_table_and_brjt.mir?rev=368274&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/jump_table_and_brjt.mir (added)
+++ llvm/trunk/test/CodeGen/Mips/GlobalISel/legalizer/jump_table_and_brjt.mir Thu Aug 8 03:21:12 2019
@@ -0,0 +1,213 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+--- |
+
+ define i32 @mod4_0_to_11(i32 %a) {
+ entry:
+ switch i32 %a, label %sw.default [
+ i32 0, label %sw.bb
+ i32 4, label %sw.bb
+ i32 1, label %sw.bb1
+ i32 5, label %sw.bb1
+ i32 2, label %sw.bb2
+ i32 6, label %sw.bb2
+ i32 3, label %sw.bb3
+ i32 7, label %sw.bb3
+ ]
+
+ sw.bb: ; preds = %entry, %entry
+ ret i32 0
+
+ sw.bb1: ; preds = %entry, %entry
+ ret i32 1
+
+ sw.bb2: ; preds = %entry, %entry
+ ret i32 2
+
+ sw.bb3: ; preds = %entry, %entry
+ ret i32 3
+
+ sw.default: ; preds = %entry
+ br label %sw.epilog
+
+ sw.epilog: ; preds = %sw.default
+ switch i32 %a, label %sw.default8 [
+ i32 8, label %sw.bb4
+ i32 9, label %sw.bb5
+ i32 10, label %sw.bb6
+ i32 11, label %sw.bb7
+ ]
+
+ sw.bb4: ; preds = %sw.epilog
+ ret i32 0
+
+ sw.bb5: ; preds = %sw.epilog
+ ret i32 1
+
+ sw.bb6: ; preds = %sw.epilog
+ ret i32 2
+
+ sw.bb7: ; preds = %sw.epilog
+ ret i32 3
+
+ sw.default8: ; preds = %sw.epilog
+ ret i32 -1
+ }
+
+...
+---
+name: mod4_0_to_11
+alignment: 2
+tracksRegLiveness: true
+jumpTable:
+ kind: block-address
+ entries:
+ - id: 0
+ blocks: [ '%bb.2', '%bb.3', '%bb.4', '%bb.5', '%bb.2', '%bb.3',
+ '%bb.4', '%bb.5' ]
+ - id: 1
+ blocks: [ '%bb.8', '%bb.9', '%bb.10', '%bb.11' ]
+body: |
+ ; MIPS32-LABEL: name: mod4_0_to_11
+ ; MIPS32: bb.0.entry:
+ ; MIPS32: successors: %bb.6(0x40000000), %bb.1(0x40000000)
+ ; MIPS32: liveins: $a0
+ ; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
+ ; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 7
+ ; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
+ ; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
+ ; MIPS32: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; MIPS32: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; MIPS32: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
+ ; MIPS32: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; MIPS32: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[C6]]
+ ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
+ ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
+ ; MIPS32: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY1]](s32), [[COPY2]]
+ ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ICMP]](s32)
+ ; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C3]]
+ ; MIPS32: G_BRCOND [[AND]](s32), %bb.6
+ ; MIPS32: bb.1.entry:
+ ; MIPS32: successors: %bb.2(0x20000000), %bb.3(0x20000000), %bb.4(0x20000000), %bb.5(0x20000000)
+ ; MIPS32: [[JUMP_TABLE:%[0-9]+]]:_(p0) = G_JUMP_TABLE %jump-table.0
+ ; MIPS32: G_BRJT [[JUMP_TABLE]](p0), %jump-table.0, [[COPY1]](s32)
+ ; MIPS32: bb.2.sw.bb:
+ ; MIPS32: $v0 = COPY [[C4]](s32)
+ ; MIPS32: RetRA implicit $v0
+ ; MIPS32: bb.3.sw.bb1:
+ ; MIPS32: $v0 = COPY [[C3]](s32)
+ ; MIPS32: RetRA implicit $v0
+ ; MIPS32: bb.4.sw.bb2:
+ ; MIPS32: $v0 = COPY [[C2]](s32)
+ ; MIPS32: RetRA implicit $v0
+ ; MIPS32: bb.5.sw.bb3:
+ ; MIPS32: $v0 = COPY [[C1]](s32)
+ ; MIPS32: RetRA implicit $v0
+ ; MIPS32: bb.6.sw.default:
+ ; MIPS32: successors: %bb.7(0x80000000)
+ ; MIPS32: bb.7.sw.epilog:
+ ; MIPS32: successors: %bb.13(0x40000000), %bb.8(0x40000000)
+ ; MIPS32: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+ ; MIPS32: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[C7]]
+ ; MIPS32: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB1]](s32)
+ ; MIPS32: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; MIPS32: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[COPY4]](s32), [[COPY5]]
+ ; MIPS32: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; MIPS32: [[COPY6:%[0-9]+]]:_(s32) = COPY [[ICMP1]](s32)
+ ; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C8]]
+ ; MIPS32: G_BRCOND [[AND1]](s32), %bb.13
+ ; MIPS32: bb.8.sw.epilog:
+ ; MIPS32: successors: %bb.9(0x20000000), %bb.10(0x20000000), %bb.11(0x20000000), %bb.12(0x20000000)
+ ; MIPS32: [[JUMP_TABLE1:%[0-9]+]]:_(p0) = G_JUMP_TABLE %jump-table.1
+ ; MIPS32: G_BRJT [[JUMP_TABLE1]](p0), %jump-table.1, [[COPY4]](s32)
+ ; MIPS32: bb.9.sw.bb4:
+ ; MIPS32: $v0 = COPY [[C4]](s32)
+ ; MIPS32: RetRA implicit $v0
+ ; MIPS32: bb.10.sw.bb5:
+ ; MIPS32: $v0 = COPY [[C3]](s32)
+ ; MIPS32: RetRA implicit $v0
+ ; MIPS32: bb.11.sw.bb6:
+ ; MIPS32: $v0 = COPY [[C2]](s32)
+ ; MIPS32: RetRA implicit $v0
+ ; MIPS32: bb.12.sw.bb7:
+ ; MIPS32: $v0 = COPY [[C1]](s32)
+ ; MIPS32: RetRA implicit $v0
+ ; MIPS32: bb.13.sw.default8:
+ ; MIPS32: $v0 = COPY [[C5]](s32)
+ ; MIPS32: RetRA implicit $v0
+ bb.1.entry:
+ liveins: $a0
+
+ %0:_(s32) = COPY $a0
+ %4:_(s32) = G_CONSTANT i32 7
+ %8:_(s32) = G_CONSTANT i32 3
+ %9:_(s32) = G_CONSTANT i32 2
+ %10:_(s32) = G_CONSTANT i32 1
+ %11:_(s32) = G_CONSTANT i32 0
+ %18:_(s32) = G_CONSTANT i32 -1
+ %1:_(s32) = G_CONSTANT i32 0
+ %2:_(s32) = G_SUB %0, %1
+ %3:_(s32) = COPY %2(s32)
+ %5:_(s32) = COPY %4(s32)
+ %6:_(s1) = G_ICMP intpred(ugt), %3(s32), %5
+ G_BRCOND %6(s1), %bb.6
+
+ bb.13.entry:
+ successors: %bb.2, %bb.3, %bb.4, %bb.5
+
+ %7:_(p0) = G_JUMP_TABLE %jump-table.0
+ G_BRJT %7(p0), %jump-table.0, %3(s32)
+
+ bb.2.sw.bb:
+ $v0 = COPY %11(s32)
+ RetRA implicit $v0
+
+ bb.3.sw.bb1:
+ $v0 = COPY %10(s32)
+ RetRA implicit $v0
+
+ bb.4.sw.bb2:
+ $v0 = COPY %9(s32)
+ RetRA implicit $v0
+
+ bb.5.sw.bb3:
+ $v0 = COPY %8(s32)
+ RetRA implicit $v0
+
+ bb.6.sw.default:
+
+ bb.7.sw.epilog:
+ %12:_(s32) = G_CONSTANT i32 8
+ %13:_(s32) = G_SUB %0, %12
+ %14:_(s32) = COPY %13(s32)
+ %15:_(s32) = COPY %8(s32)
+ %16:_(s1) = G_ICMP intpred(ugt), %14(s32), %15
+ G_BRCOND %16(s1), %bb.12
+
+ bb.14.sw.epilog:
+ successors: %bb.8, %bb.9, %bb.10, %bb.11
+
+ %17:_(p0) = G_JUMP_TABLE %jump-table.1
+ G_BRJT %17(p0), %jump-table.1, %14(s32)
+
+ bb.8.sw.bb4:
+ $v0 = COPY %11(s32)
+ RetRA implicit $v0
+
+ bb.9.sw.bb5:
+ $v0 = COPY %10(s32)
+ RetRA implicit $v0
+
+ bb.10.sw.bb6:
+ $v0 = COPY %9(s32)
+ RetRA implicit $v0
+
+ bb.11.sw.bb7:
+ $v0 = COPY %8(s32)
+ RetRA implicit $v0
+
+ bb.12.sw.default8:
+ $v0 = COPY %18(s32)
+ RetRA implicit $v0
+
+...
Added: llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/jump_table_and_brjt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/jump_table_and_brjt.ll?rev=368274&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/jump_table_and_brjt.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/GlobalISel/llvm-ir/jump_table_and_brjt.ll Thu Aug 8 03:21:12 2019
@@ -0,0 +1,288 @@
+; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32
+; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -relocation-model=pic -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32_PIC
+
+define i32 @mod4_0_to_11(i32 %a) {
+; MIPS32-LABEL: mod4_0_to_11:
+; MIPS32: # %bb.0: # %entry
+; MIPS32-NEXT: addiu $sp, $sp, -32
+; MIPS32-NEXT: .cfi_def_cfa_offset 32
+; MIPS32-NEXT: ori $1, $zero, 7
+; MIPS32-NEXT: ori $2, $zero, 3
+; MIPS32-NEXT: ori $3, $zero, 2
+; MIPS32-NEXT: ori $5, $zero, 1
+; MIPS32-NEXT: ori $6, $zero, 0
+; MIPS32-NEXT: addiu $7, $zero, 65535
+; MIPS32-NEXT: ori $8, $zero, 0
+; MIPS32-NEXT: subu $8, $4, $8
+; MIPS32-NEXT: sltu $1, $1, $8
+; MIPS32-NEXT: and $1, $1, $5
+; MIPS32-NEXT: sw $4, 28($sp) # 4-byte Folded Spill
+; MIPS32-NEXT: sw $2, 24($sp) # 4-byte Folded Spill
+; MIPS32-NEXT: sw $3, 20($sp) # 4-byte Folded Spill
+; MIPS32-NEXT: sw $5, 16($sp) # 4-byte Folded Spill
+; MIPS32-NEXT: sw $6, 12($sp) # 4-byte Folded Spill
+; MIPS32-NEXT: sw $7, 8($sp) # 4-byte Folded Spill
+; MIPS32-NEXT: sw $8, 4($sp) # 4-byte Folded Spill
+; MIPS32-NEXT: bnez $1, $BB0_6
+; MIPS32-NEXT: nop
+; MIPS32-NEXT: $BB0_1: # %entry
+; MIPS32-NEXT: lui $1, %hi($JTI0_0)
+; MIPS32-NEXT: lw $2, 4($sp) # 4-byte Folded Reload
+; MIPS32-NEXT: sll $3, $2, 2
+; MIPS32-NEXT: addu $1, $1, $3
+; MIPS32-NEXT: lw $1, %lo($JTI0_0)($1)
+; MIPS32-NEXT: jr $1
+; MIPS32-NEXT: nop
+; MIPS32-NEXT: $BB0_2: # %sw.bb
+; MIPS32-NEXT: lw $2, 12($sp) # 4-byte Folded Reload
+; MIPS32-NEXT: addiu $sp, $sp, 32
+; MIPS32-NEXT: jr $ra
+; MIPS32-NEXT: nop
+; MIPS32-NEXT: $BB0_3: # %sw.bb1
+; MIPS32-NEXT: lw $2, 16($sp) # 4-byte Folded Reload
+; MIPS32-NEXT: addiu $sp, $sp, 32
+; MIPS32-NEXT: jr $ra
+; MIPS32-NEXT: nop
+; MIPS32-NEXT: $BB0_4: # %sw.bb2
+; MIPS32-NEXT: lw $2, 20($sp) # 4-byte Folded Reload
+; MIPS32-NEXT: addiu $sp, $sp, 32
+; MIPS32-NEXT: jr $ra
+; MIPS32-NEXT: nop
+; MIPS32-NEXT: $BB0_5: # %sw.bb3
+; MIPS32-NEXT: lw $2, 24($sp) # 4-byte Folded Reload
+; MIPS32-NEXT: addiu $sp, $sp, 32
+; MIPS32-NEXT: jr $ra
+; MIPS32-NEXT: nop
+; MIPS32-NEXT: $BB0_6: # %sw.default
+; MIPS32-NEXT: .insn
+; MIPS32-NEXT: # %bb.7: # %sw.epilog
+; MIPS32-NEXT: ori $1, $zero, 8
+; MIPS32-NEXT: lw $2, 28($sp) # 4-byte Folded Reload
+; MIPS32-NEXT: subu $1, $2, $1
+; MIPS32-NEXT: lw $3, 24($sp) # 4-byte Folded Reload
+; MIPS32-NEXT: sltu $4, $3, $1
+; MIPS32-NEXT: ori $5, $zero, 1
+; MIPS32-NEXT: and $4, $4, $5
+; MIPS32-NEXT: sw $1, 0($sp) # 4-byte Folded Spill
+; MIPS32-NEXT: bnez $4, $BB0_13
+; MIPS32-NEXT: nop
+; MIPS32-NEXT: $BB0_8: # %sw.epilog
+; MIPS32-NEXT: lui $1, %hi($JTI0_1)
+; MIPS32-NEXT: lw $2, 0($sp) # 4-byte Folded Reload
+; MIPS32-NEXT: sll $3, $2, 2
+; MIPS32-NEXT: addu $1, $1, $3
+; MIPS32-NEXT: lw $1, %lo($JTI0_1)($1)
+; MIPS32-NEXT: jr $1
+; MIPS32-NEXT: nop
+; MIPS32-NEXT: $BB0_9: # %sw.bb4
+; MIPS32-NEXT: lw $2, 12($sp) # 4-byte Folded Reload
+; MIPS32-NEXT: addiu $sp, $sp, 32
+; MIPS32-NEXT: jr $ra
+; MIPS32-NEXT: nop
+; MIPS32-NEXT: $BB0_10: # %sw.bb5
+; MIPS32-NEXT: lw $2, 16($sp) # 4-byte Folded Reload
+; MIPS32-NEXT: addiu $sp, $sp, 32
+; MIPS32-NEXT: jr $ra
+; MIPS32-NEXT: nop
+; MIPS32-NEXT: $BB0_11: # %sw.bb6
+; MIPS32-NEXT: lw $2, 20($sp) # 4-byte Folded Reload
+; MIPS32-NEXT: addiu $sp, $sp, 32
+; MIPS32-NEXT: jr $ra
+; MIPS32-NEXT: nop
+; MIPS32-NEXT: $BB0_12: # %sw.bb7
+; MIPS32-NEXT: lw $2, 24($sp) # 4-byte Folded Reload
+; MIPS32-NEXT: addiu $sp, $sp, 32
+; MIPS32-NEXT: jr $ra
+; MIPS32-NEXT: nop
+; MIPS32-NEXT: $BB0_13: # %sw.default8
+; MIPS32-NEXT: lw $2, 8($sp) # 4-byte Folded Reload
+; MIPS32-NEXT: addiu $sp, $sp, 32
+; MIPS32-NEXT: jr $ra
+; MIPS32-NEXT: nop
+; MIPS32: $JTI0_0:
+; MIPS32-NEXT: .4byte ($BB0_2)
+; MIPS32-NEXT: .4byte ($BB0_3)
+; MIPS32-NEXT: .4byte ($BB0_4)
+; MIPS32-NEXT: .4byte ($BB0_5)
+; MIPS32-NEXT: .4byte ($BB0_2)
+; MIPS32-NEXT: .4byte ($BB0_3)
+; MIPS32-NEXT: .4byte ($BB0_4)
+; MIPS32-NEXT: .4byte ($BB0_5)
+; MIPS32-NEXT: $JTI0_1:
+; MIPS32-NEXT: .4byte ($BB0_9)
+; MIPS32-NEXT: .4byte ($BB0_10)
+; MIPS32-NEXT: .4byte ($BB0_11)
+; MIPS32-NEXT: .4byte ($BB0_12)
+
+;
+; MIPS32_PIC-LABEL: mod4_0_to_11:
+; MIPS32_PIC: # %bb.0: # %entry
+; MIPS32_PIC-NEXT: lui $2, %hi(_gp_disp)
+; MIPS32_PIC-NEXT: addiu $2, $2, %lo(_gp_disp)
+; MIPS32_PIC-NEXT: addiu $sp, $sp, -40
+; MIPS32_PIC-NEXT: .cfi_def_cfa_offset 40
+; MIPS32_PIC-NEXT: addu $1, $2, $25
+; MIPS32_PIC-NEXT: ori $2, $zero, 7
+; MIPS32_PIC-NEXT: ori $3, $zero, 3
+; MIPS32_PIC-NEXT: ori $5, $zero, 2
+; MIPS32_PIC-NEXT: ori $6, $zero, 1
+; MIPS32_PIC-NEXT: ori $7, $zero, 0
+; MIPS32_PIC-NEXT: addiu $8, $zero, 65535
+; MIPS32_PIC-NEXT: ori $9, $zero, 0
+; MIPS32_PIC-NEXT: subu $9, $4, $9
+; MIPS32_PIC-NEXT: sltu $2, $2, $9
+; MIPS32_PIC-NEXT: and $2, $2, $6
+; MIPS32_PIC-NEXT: sw $1, 36($sp) # 4-byte Folded Spill
+; MIPS32_PIC-NEXT: sw $4, 32($sp) # 4-byte Folded Spill
+; MIPS32_PIC-NEXT: sw $3, 28($sp) # 4-byte Folded Spill
+; MIPS32_PIC-NEXT: sw $5, 24($sp) # 4-byte Folded Spill
+; MIPS32_PIC-NEXT: sw $6, 20($sp) # 4-byte Folded Spill
+; MIPS32_PIC-NEXT: sw $7, 16($sp) # 4-byte Folded Spill
+; MIPS32_PIC-NEXT: sw $8, 12($sp) # 4-byte Folded Spill
+; MIPS32_PIC-NEXT: sw $9, 8($sp) # 4-byte Folded Spill
+; MIPS32_PIC-NEXT: bnez $2, $BB0_6
+; MIPS32_PIC-NEXT: nop
+; MIPS32_PIC-NEXT: $BB0_1: # %entry
+; MIPS32_PIC-NEXT: lw $1, 36($sp) # 4-byte Folded Reload
+; MIPS32_PIC-NEXT: lw $2, %got($JTI0_0)($1)
+; MIPS32_PIC-NEXT: lw $3, 8($sp) # 4-byte Folded Reload
+; MIPS32_PIC-NEXT: sll $4, $3, 2
+; MIPS32_PIC-NEXT: addu $2, $2, $4
+; MIPS32_PIC-NEXT: lw $2, %lo($JTI0_0)($2)
+; MIPS32_PIC-NEXT: addu $2, $2, $1
+; MIPS32_PIC-NEXT: jr $2
+; MIPS32_PIC-NEXT: nop
+; MIPS32_PIC-NEXT: $BB0_2: # %sw.bb
+; MIPS32_PIC-NEXT: lw $2, 16($sp) # 4-byte Folded Reload
+; MIPS32_PIC-NEXT: addiu $sp, $sp, 40
+; MIPS32_PIC-NEXT: jr $ra
+; MIPS32_PIC-NEXT: nop
+; MIPS32_PIC-NEXT: $BB0_3: # %sw.bb1
+; MIPS32_PIC-NEXT: lw $2, 20($sp) # 4-byte Folded Reload
+; MIPS32_PIC-NEXT: addiu $sp, $sp, 40
+; MIPS32_PIC-NEXT: jr $ra
+; MIPS32_PIC-NEXT: nop
+; MIPS32_PIC-NEXT: $BB0_4: # %sw.bb2
+; MIPS32_PIC-NEXT: lw $2, 24($sp) # 4-byte Folded Reload
+; MIPS32_PIC-NEXT: addiu $sp, $sp, 40
+; MIPS32_PIC-NEXT: jr $ra
+; MIPS32_PIC-NEXT: nop
+; MIPS32_PIC-NEXT: $BB0_5: # %sw.bb3
+; MIPS32_PIC-NEXT: lw $2, 28($sp) # 4-byte Folded Reload
+; MIPS32_PIC-NEXT: addiu $sp, $sp, 40
+; MIPS32_PIC-NEXT: jr $ra
+; MIPS32_PIC-NEXT: nop
+; MIPS32_PIC-NEXT: $BB0_6: # %sw.default
+; MIPS32_PIC-NEXT: .insn
+; MIPS32_PIC-NEXT: # %bb.7: # %sw.epilog
+; MIPS32_PIC-NEXT: ori $1, $zero, 8
+; MIPS32_PIC-NEXT: lw $2, 32($sp) # 4-byte Folded Reload
+; MIPS32_PIC-NEXT: subu $1, $2, $1
+; MIPS32_PIC-NEXT: lw $3, 28($sp) # 4-byte Folded Reload
+; MIPS32_PIC-NEXT: sltu $4, $3, $1
+; MIPS32_PIC-NEXT: ori $5, $zero, 1
+; MIPS32_PIC-NEXT: and $4, $4, $5
+; MIPS32_PIC-NEXT: sw $1, 4($sp) # 4-byte Folded Spill
+; MIPS32_PIC-NEXT: bnez $4, $BB0_13
+; MIPS32_PIC-NEXT: nop
+; MIPS32_PIC-NEXT: $BB0_8: # %sw.epilog
+; MIPS32_PIC-NEXT: lw $1, 36($sp) # 4-byte Folded Reload
+; MIPS32_PIC-NEXT: lw $2, %got($JTI0_1)($1)
+; MIPS32_PIC-NEXT: lw $3, 4($sp) # 4-byte Folded Reload
+; MIPS32_PIC-NEXT: sll $4, $3, 2
+; MIPS32_PIC-NEXT: addu $2, $2, $4
+; MIPS32_PIC-NEXT: lw $2, %lo($JTI0_1)($2)
+; MIPS32_PIC-NEXT: addu $2, $2, $1
+; MIPS32_PIC-NEXT: jr $2
+; MIPS32_PIC-NEXT: nop
+; MIPS32_PIC-NEXT: $BB0_9: # %sw.bb4
+; MIPS32_PIC-NEXT: lw $2, 16($sp) # 4-byte Folded Reload
+; MIPS32_PIC-NEXT: addiu $sp, $sp, 40
+; MIPS32_PIC-NEXT: jr $ra
+; MIPS32_PIC-NEXT: nop
+; MIPS32_PIC-NEXT: $BB0_10: # %sw.bb5
+; MIPS32_PIC-NEXT: lw $2, 20($sp) # 4-byte Folded Reload
+; MIPS32_PIC-NEXT: addiu $sp, $sp, 40
+; MIPS32_PIC-NEXT: jr $ra
+; MIPS32_PIC-NEXT: nop
+; MIPS32_PIC-NEXT: $BB0_11: # %sw.bb6
+; MIPS32_PIC-NEXT: lw $2, 24($sp) # 4-byte Folded Reload
+; MIPS32_PIC-NEXT: addiu $sp, $sp, 40
+; MIPS32_PIC-NEXT: jr $ra
+; MIPS32_PIC-NEXT: nop
+; MIPS32_PIC-NEXT: $BB0_12: # %sw.bb7
+; MIPS32_PIC-NEXT: lw $2, 28($sp) # 4-byte Folded Reload
+; MIPS32_PIC-NEXT: addiu $sp, $sp, 40
+; MIPS32_PIC-NEXT: jr $ra
+; MIPS32_PIC-NEXT: nop
+; MIPS32_PIC-NEXT: $BB0_13: # %sw.default8
+; MIPS32_PIC-NEXT: lw $2, 12($sp) # 4-byte Folded Reload
+; MIPS32_PIC-NEXT: addiu $sp, $sp, 40
+; MIPS32_PIC-NEXT: jr $ra
+; MIPS32_PIC-NEXT: nop
+; MIPS32_PIC: $JTI0_0:
+; MIPS32_PIC-NEXT: .gpword ($BB0_2)
+; MIPS32_PIC-NEXT: .gpword ($BB0_3)
+; MIPS32_PIC-NEXT: .gpword ($BB0_4)
+; MIPS32_PIC-NEXT: .gpword ($BB0_5)
+; MIPS32_PIC-NEXT: .gpword ($BB0_2)
+; MIPS32_PIC-NEXT: .gpword ($BB0_3)
+; MIPS32_PIC-NEXT: .gpword ($BB0_4)
+; MIPS32_PIC-NEXT: .gpword ($BB0_5)
+; MIPS32_PIC-NEXT: $JTI0_1:
+; MIPS32_PIC-NEXT: .gpword ($BB0_9)
+; MIPS32_PIC-NEXT: .gpword ($BB0_10)
+; MIPS32_PIC-NEXT: .gpword ($BB0_11)
+; MIPS32_PIC-NEXT: .gpword ($BB0_12)
+
+entry:
+ switch i32 %a, label %sw.default [
+ i32 0, label %sw.bb
+ i32 4, label %sw.bb
+ i32 1, label %sw.bb1
+ i32 5, label %sw.bb1
+ i32 2, label %sw.bb2
+ i32 6, label %sw.bb2
+ i32 3, label %sw.bb3
+ i32 7, label %sw.bb3
+ ]
+
+sw.bb: ; preds = %entry, %entry
+ ret i32 0
+
+sw.bb1: ; preds = %entry, %entry
+ ret i32 1
+
+sw.bb2: ; preds = %entry, %entry
+ ret i32 2
+
+sw.bb3: ; preds = %entry, %entry
+ ret i32 3
+
+sw.default: ; preds = %entry
+ br label %sw.epilog
+
+sw.epilog: ; preds = %sw.default
+ switch i32 %a, label %sw.default8 [
+ i32 8, label %sw.bb4
+ i32 9, label %sw.bb5
+ i32 10, label %sw.bb6
+ i32 11, label %sw.bb7
+ ]
+
+sw.bb4: ; preds = %sw.epilog
+ ret i32 0
+
+sw.bb5: ; preds = %sw.epilog
+ ret i32 1
+
+sw.bb6: ; preds = %sw.epilog
+ ret i32 2
+
+sw.bb7: ; preds = %sw.epilog
+ ret i32 3
+
+sw.default8: ; preds = %sw.epilog
+ ret i32 -1
+
+}
Added: llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/jump_table_and_brjt.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/jump_table_and_brjt.mir?rev=368274&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/jump_table_and_brjt.mir (added)
+++ llvm/trunk/test/CodeGen/Mips/GlobalISel/regbankselect/jump_table_and_brjt.mir Thu Aug 8 03:21:12 2019
@@ -0,0 +1,219 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
+--- |
+
+ define i32 @mod4_0_to_11(i32 %a) {
+ entry:
+ switch i32 %a, label %sw.default [
+ i32 0, label %sw.bb
+ i32 4, label %sw.bb
+ i32 1, label %sw.bb1
+ i32 5, label %sw.bb1
+ i32 2, label %sw.bb2
+ i32 6, label %sw.bb2
+ i32 3, label %sw.bb3
+ i32 7, label %sw.bb3
+ ]
+
+ sw.bb: ; preds = %entry, %entry
+ ret i32 0
+
+ sw.bb1: ; preds = %entry, %entry
+ ret i32 1
+
+ sw.bb2: ; preds = %entry, %entry
+ ret i32 2
+
+ sw.bb3: ; preds = %entry, %entry
+ ret i32 3
+
+ sw.default: ; preds = %entry
+ br label %sw.epilog
+
+ sw.epilog: ; preds = %sw.default
+ switch i32 %a, label %sw.default8 [
+ i32 8, label %sw.bb4
+ i32 9, label %sw.bb5
+ i32 10, label %sw.bb6
+ i32 11, label %sw.bb7
+ ]
+
+ sw.bb4: ; preds = %sw.epilog
+ ret i32 0
+
+ sw.bb5: ; preds = %sw.epilog
+ ret i32 1
+
+ sw.bb6: ; preds = %sw.epilog
+ ret i32 2
+
+ sw.bb7: ; preds = %sw.epilog
+ ret i32 3
+
+ sw.default8: ; preds = %sw.epilog
+ ret i32 -1
+ }
+
+...
+---
+name: mod4_0_to_11
+alignment: 2
+legalized: true
+tracksRegLiveness: true
+jumpTable:
+ kind: block-address
+ entries:
+ - id: 0
+ blocks: [ '%bb.2', '%bb.3', '%bb.4', '%bb.5', '%bb.2', '%bb.3',
+ '%bb.4', '%bb.5' ]
+ - id: 1
+ blocks: [ '%bb.8', '%bb.9', '%bb.10', '%bb.11' ]
+body: |
+ ; MIPS32-LABEL: name: mod4_0_to_11
+ ; MIPS32: bb.0.entry:
+ ; MIPS32: successors: %bb.6(0x40000000), %bb.1(0x40000000)
+ ; MIPS32: liveins: $a0
+ ; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
+ ; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 7
+ ; MIPS32: [[C1:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 3
+ ; MIPS32: [[C2:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 2
+ ; MIPS32: [[C3:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
+ ; MIPS32: [[C4:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0
+ ; MIPS32: [[C5:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 -1
+ ; MIPS32: [[C6:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0
+ ; MIPS32: [[SUB:%[0-9]+]]:gprb(s32) = G_SUB [[COPY]], [[C6]]
+ ; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY [[SUB]](s32)
+ ; MIPS32: [[COPY2:%[0-9]+]]:gprb(s32) = COPY [[C]](s32)
+ ; MIPS32: [[ICMP:%[0-9]+]]:gprb(s32) = G_ICMP intpred(ugt), [[COPY1]](s32), [[COPY2]]
+ ; MIPS32: [[COPY3:%[0-9]+]]:gprb(s32) = COPY [[ICMP]](s32)
+ ; MIPS32: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY3]], [[C3]]
+ ; MIPS32: G_BRCOND [[AND]](s32), %bb.6
+ ; MIPS32: bb.1.entry:
+ ; MIPS32: successors: %bb.2(0x20000000), %bb.3(0x20000000), %bb.4(0x20000000), %bb.5(0x20000000)
+ ; MIPS32: [[JUMP_TABLE:%[0-9]+]]:gprb(p0) = G_JUMP_TABLE %jump-table.0
+ ; MIPS32: G_BRJT [[JUMP_TABLE]](p0), %jump-table.0, [[COPY1]](s32)
+ ; MIPS32: bb.2.sw.bb:
+ ; MIPS32: $v0 = COPY [[C4]](s32)
+ ; MIPS32: RetRA implicit $v0
+ ; MIPS32: bb.3.sw.bb1:
+ ; MIPS32: $v0 = COPY [[C3]](s32)
+ ; MIPS32: RetRA implicit $v0
+ ; MIPS32: bb.4.sw.bb2:
+ ; MIPS32: $v0 = COPY [[C2]](s32)
+ ; MIPS32: RetRA implicit $v0
+ ; MIPS32: bb.5.sw.bb3:
+ ; MIPS32: $v0 = COPY [[C1]](s32)
+ ; MIPS32: RetRA implicit $v0
+ ; MIPS32: bb.6.sw.default:
+ ; MIPS32: successors: %bb.7(0x80000000)
+ ; MIPS32: bb.7.sw.epilog:
+ ; MIPS32: successors: %bb.13(0x40000000), %bb.8(0x40000000)
+ ; MIPS32: [[C7:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 8
+ ; MIPS32: [[SUB1:%[0-9]+]]:gprb(s32) = G_SUB [[COPY]], [[C7]]
+ ; MIPS32: [[COPY4:%[0-9]+]]:gprb(s32) = COPY [[SUB1]](s32)
+ ; MIPS32: [[COPY5:%[0-9]+]]:gprb(s32) = COPY [[C1]](s32)
+ ; MIPS32: [[ICMP1:%[0-9]+]]:gprb(s32) = G_ICMP intpred(ugt), [[COPY4]](s32), [[COPY5]]
+ ; MIPS32: [[C8:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 1
+ ; MIPS32: [[COPY6:%[0-9]+]]:gprb(s32) = COPY [[ICMP1]](s32)
+ ; MIPS32: [[AND1:%[0-9]+]]:gprb(s32) = G_AND [[COPY6]], [[C8]]
+ ; MIPS32: G_BRCOND [[AND1]](s32), %bb.13
+ ; MIPS32: bb.8.sw.epilog:
+ ; MIPS32: successors: %bb.9(0x20000000), %bb.10(0x20000000), %bb.11(0x20000000), %bb.12(0x20000000)
+ ; MIPS32: [[JUMP_TABLE1:%[0-9]+]]:gprb(p0) = G_JUMP_TABLE %jump-table.1
+ ; MIPS32: G_BRJT [[JUMP_TABLE1]](p0), %jump-table.1, [[COPY4]](s32)
+ ; MIPS32: bb.9.sw.bb4:
+ ; MIPS32: $v0 = COPY [[C4]](s32)
+ ; MIPS32: RetRA implicit $v0
+ ; MIPS32: bb.10.sw.bb5:
+ ; MIPS32: $v0 = COPY [[C3]](s32)
+ ; MIPS32: RetRA implicit $v0
+ ; MIPS32: bb.11.sw.bb6:
+ ; MIPS32: $v0 = COPY [[C2]](s32)
+ ; MIPS32: RetRA implicit $v0
+ ; MIPS32: bb.12.sw.bb7:
+ ; MIPS32: $v0 = COPY [[C1]](s32)
+ ; MIPS32: RetRA implicit $v0
+ ; MIPS32: bb.13.sw.default8:
+ ; MIPS32: $v0 = COPY [[C5]](s32)
+ ; MIPS32: RetRA implicit $v0
+ bb.1.entry:
+ liveins: $a0
+
+ %0:_(s32) = COPY $a0
+ %4:_(s32) = G_CONSTANT i32 7
+ %8:_(s32) = G_CONSTANT i32 3
+ %9:_(s32) = G_CONSTANT i32 2
+ %10:_(s32) = G_CONSTANT i32 1
+ %11:_(s32) = G_CONSTANT i32 0
+ %18:_(s32) = G_CONSTANT i32 -1
+ %1:_(s32) = G_CONSTANT i32 0
+ %2:_(s32) = G_SUB %0, %1
+ %3:_(s32) = COPY %2(s32)
+ %5:_(s32) = COPY %4(s32)
+ %22:_(s32) = G_ICMP intpred(ugt), %3(s32), %5
+ %23:_(s32) = COPY %22(s32)
+ %21:_(s32) = G_AND %23, %10
+ G_BRCOND %21(s32), %bb.6
+
+ bb.13.entry:
+ successors: %bb.2, %bb.3, %bb.4, %bb.5
+
+ %7:_(p0) = G_JUMP_TABLE %jump-table.0
+ G_BRJT %7(p0), %jump-table.0, %3(s32)
+
+ bb.2.sw.bb:
+ $v0 = COPY %11(s32)
+ RetRA implicit $v0
+
+ bb.3.sw.bb1:
+ $v0 = COPY %10(s32)
+ RetRA implicit $v0
+
+ bb.4.sw.bb2:
+ $v0 = COPY %9(s32)
+ RetRA implicit $v0
+
+ bb.5.sw.bb3:
+ $v0 = COPY %8(s32)
+ RetRA implicit $v0
+
+ bb.6.sw.default:
+
+ bb.7.sw.epilog:
+ %12:_(s32) = G_CONSTANT i32 8
+ %13:_(s32) = G_SUB %0, %12
+ %14:_(s32) = COPY %13(s32)
+ %15:_(s32) = COPY %8(s32)
+ %20:_(s32) = G_ICMP intpred(ugt), %14(s32), %15
+ %24:_(s32) = G_CONSTANT i32 1
+ %25:_(s32) = COPY %20(s32)
+ %19:_(s32) = G_AND %25, %24
+ G_BRCOND %19(s32), %bb.12
+
+ bb.14.sw.epilog:
+ successors: %bb.8, %bb.9, %bb.10, %bb.11
+
+ %17:_(p0) = G_JUMP_TABLE %jump-table.1
+ G_BRJT %17(p0), %jump-table.1, %14(s32)
+
+ bb.8.sw.bb4:
+ $v0 = COPY %11(s32)
+ RetRA implicit $v0
+
+ bb.9.sw.bb5:
+ $v0 = COPY %10(s32)
+ RetRA implicit $v0
+
+ bb.10.sw.bb6:
+ $v0 = COPY %9(s32)
+ RetRA implicit $v0
+
+ bb.11.sw.bb7:
+ $v0 = COPY %8(s32)
+ RetRA implicit $v0
+
+ bb.12.sw.default8:
+ $v0 = COPY %18(s32)
+ RetRA implicit $v0
+
+...
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