[PATCH] D65583: [ARM] MVE big endian loads/stores

[Simon Tatham via Phabricator via llvm-commits]

simon_tatham added inline comments.


================
Comment at: llvm/lib/Target/ARM/ARMInstrMVE.td:4789
+  def  : Pat<(v4i1 (load t2addrmode_imm7<2>:$addr)),
+             (v4i1 (VLDR_P0_off t2addrmode_imm7<2>:$addr))>;
 }
----------------
samparker wrote:
> dmgreen wrote:
> > simon_tatham wrote:
> > > samparker wrote:
> > > > Do we support v2i1 as well?
> > > Currently, v2i1 isn't listed among the vector-of-i1 types that are legal in the VCCR regclass, so it probably wouldn't help to add a pattern for it here.
> > > 
> > > I have a small patch that adds it in various other places, as part of my unfinished prototype for the ACLE MVE intrinsics support. If it's becoming urgent, I could easily pull that patch out and submit it before I get the rest finished?
> > I have not added v2i1 to anything yet. It is not usually very useful, as we do not support any of the cmp's needed to produce it. Adding it sound like the kind of thing that would need a lot of testing.
> Great, sounds like a good thing to get in so we can decouple autoveec work from intrinsic support.
No sooner said: D65929 is up for review.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D65583/new/

https://reviews.llvm.org/D65583