[PATCH] D65873: [ARM] Fix encoding of APSR in CLRM instruction

[Momchil Velikov via Phabricator via llvm-commits]

chill created this revision.
Herald added subscribers: llvm-commits, hiraditya, kristof.beyls, javed.absar.
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The APSR is encoded by setting bit 15 in the register list of the CLRM
 instruction (cf. https://static.docs.arm.com/ddi0553/bh/DDI0553B_h_armv8m_arm.pdf).

Encoding APSR as 1 causes a bogus duplicated register warning and one of the registers ( r1 or apsr) is dropped, e.g.

$ llvm-mc --triple thumbv8.1m.main --show-encoding <<< 'clrm {apsr,r1,r0}'
	.text
<stdin>:1:12: warning: duplicated register (r1) in register list
clrm {apsr,r1,r0}

  ^

clrm		{r0, apsr}      @ encoding: [0x9f,0xe8,0x01,0x80]


https://reviews.llvm.org/D65873

Files:
  llvm/lib/Target/ARM/ARMRegisterInfo.td
  llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
  llvm/test/MC/ARM/clrm-asm.s


Index: llvm/test/MC/ARM/clrm-asm.s
===================================================================
--- llvm/test/MC/ARM/clrm-asm.s
+++ llvm/test/MC/ARM/clrm-asm.s
@@ -9,13 +9,16 @@
 // ERROR-NOT: register list not in ascending order
 clrm {r3, r4, r1, r2}
 
-// CHECK: clrm            {r0, apsr, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, lr} @ encoding: [0x9f,0xe8,0xff,0xdf]
+// CHECK: clrm            {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, lr, apsr} @ encoding: [0x9f,0xe8,0xff,0xdf]
 clrm {r0-r12, lr, apsr}
 
-// CHECK: clrm            {apsr, lr} @ encoding: [0x9f,0xe8,0x00,0xc0]
+// CHECK: clrm            {lr, apsr} @ encoding: [0x9f,0xe8,0x00,0xc0]
 clrm {apsr, lr}
 
-// CHECK: clrm            {r0, apsr, r1, r2, r3, r4, lr} @ encoding: [0x9f,0xe8,0x1f,0xc0]
+// CHECK: clrm            {r0, r1, apsr}  @ encoding: [0x9f,0xe8,0x03,0x80]
+clrm {apsr, r1, r0}
+
+// CHECK: clrm            {r0, r1, r2, r3, r4, lr, apsr} @ encoding: [0x9f,0xe8,0x1f,0xc0]
 clrm {r0-r4, apsr, lr}
 
 // ERROR: invalid register in register list. Valid registers are r0-r12, lr/r14 and APSR.
Index: llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
===================================================================
--- llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
+++ llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
@@ -1720,7 +1720,6 @@
   unsigned Reg = MI.getOperand(Op).getReg();
   bool SPRRegs = ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg);
   bool DPRRegs = ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg);
-  bool CLRMRegs = MI.getOpcode() == ARM::t2CLRM;
 
   unsigned Binary = 0;
 
@@ -1739,21 +1738,13 @@
       Binary |= NumRegs * 2;
   } else {
     const MCRegisterInfo &MRI = *CTX.getRegisterInfo();
-    if (!CLRMRegs) {
-      assert(std::is_sorted(MI.begin() + Op, MI.end(),
-                            [&](const MCOperand &LHS, const MCOperand &RHS) {
-                              return MRI.getEncodingValue(LHS.getReg()) <
-                                     MRI.getEncodingValue(RHS.getReg());
-                            }));
-    }
-
+    assert(std::is_sorted(MI.begin() + Op, MI.end(),
+                          [&](const MCOperand &LHS, const MCOperand &RHS) {
+                            return MRI.getEncodingValue(LHS.getReg()) <
+                              MRI.getEncodingValue(RHS.getReg());
+                          }));
     for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
-      unsigned RegNo;
-      if (CLRMRegs && MI.getOperand(I).getReg() == ARM::APSR) {
-        RegNo = 15;
-      } else {
-        RegNo = MRI.getEncodingValue(MI.getOperand(I).getReg());
-      }
+      unsigned RegNo = MRI.getEncodingValue(MI.getOperand(I).getReg());
       Binary |= 1 << RegNo;
     }
   }
Index: llvm/lib/Target/ARM/ARMRegisterInfo.td
===================================================================
--- llvm/lib/Target/ARM/ARMRegisterInfo.td
+++ llvm/lib/Target/ARM/ARMRegisterInfo.td
@@ -180,7 +180,7 @@
 // models the APSR when it's accessed by some special instructions. In such cases
 // it has the same encoding as PC.
 def CPSR       : ARMReg<0,  "cpsr">;
-def APSR       : ARMReg<1,  "apsr">;
+def APSR       : ARMReg<15, "apsr">;
 def APSR_NZCV  : ARMReg<15, "apsr_nzcv">;
 def SPSR       : ARMReg<2,  "spsr">;
 def FPSCR      : ARMReg<3,  "fpscr">;


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