[llvm] r368042 - [StructurizeCFG] Enable -structurizecfg-relaxed-uniform-regions by default

Tim Renouf via llvm-commits llvm-commits at lists.llvm.org
Tue Aug 6 07:30:20 PDT 2019


Author: tpr
Date: Tue Aug  6 07:30:19 2019
New Revision: 368042

URL: http://llvm.org/viewvc/llvm-project?rev=368042&view=rev
Log:
[StructurizeCFG] Enable -structurizecfg-relaxed-uniform-regions by default

D62198 introduced an option to relax the checks for
hasOnlyUniformBranches. This commit turns the option on by default, for
better code generation in some cases in AMDGPU.

Differential Revision: https://reviews.llvm.org/D63198

Change-Id: I9cbff002a1e74d3b7eb96b4192dc8129936d537d

Modified:
    llvm/trunk/lib/Transforms/Scalar/StructurizeCFG.cpp
    llvm/trunk/test/CodeGen/AMDGPU/control-flow-optnone.ll

Modified: llvm/trunk/lib/Transforms/Scalar/StructurizeCFG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/StructurizeCFG.cpp?rev=368042&r1=368041&r2=368042&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/StructurizeCFG.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/StructurizeCFG.cpp Tue Aug  6 07:30:19 2019
@@ -65,7 +65,7 @@ static cl::opt<bool> ForceSkipUniformReg
 static cl::opt<bool>
     RelaxedUniformRegions("structurizecfg-relaxed-uniform-regions", cl::Hidden,
                           cl::desc("Allow relaxed uniform region checks"),
-                          cl::init(false));
+                          cl::init(true));
 
 // Definition of the complex types used in this pass.
 

Modified: llvm/trunk/test/CodeGen/AMDGPU/control-flow-optnone.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/control-flow-optnone.ll?rev=368042&r1=368041&r2=368042&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/control-flow-optnone.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/control-flow-optnone.ll Tue Aug  6 07:30:19 2019
@@ -15,8 +15,8 @@
 ; GCN: s_mov_b64 exec
 
 ; GCN: s_or_b64 exec, exec
-; GCN: v_cmp_eq_u32
-; GCN: s_cbranch_vccnz
+; GCN: s_cmp_eq_u32
+; GCN: s_cbranch_scc1
 ; GCN-NEXT: s_branch
 define amdgpu_kernel void @copytoreg_divergent_brcond(i32 %arg, i32 %arg1, i32 %arg2) #0 {
 bb:




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