[PATCH] D63840: [ARM] Add support for MVE pre and post inc loads and stores.

[Dave Green via Phabricator via llvm-commits]

dmgreen marked an inline comment as done.
dmgreen added inline comments.


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Comment at: llvm/include/llvm/Target/TargetSelectionDAG.td:1114
+def pre_truncstvi16 : PatFrag<(ops node:$val, node:$base, node:$offset),
+                             (pre_truncst node:$val, node:$base, node:$offset)> {
+  let IsStore = 1;
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SjoerdMeijer wrote:
> SjoerdMeijer wrote:
> > nit: indent off by 1
> same nit if I'm not mistaken
Sorry, I did mean to get to this! I need to rebase this over the bigendian code too. Let me do that now.


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Comment at: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp:1612
+
+  if (Align >= 2 && LoadedVT == MVT::v4i16 &&
+      SelectT2AddrModeImm7Offset(N, LD->getOffset(), Offset, 1)) {
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SjoerdMeijer wrote:
> dmgreen wrote:
> > SjoerdMeijer wrote:
> > > Why the >= comparisons for the alignment? Is that right?
> > The instruction (VLDRH) only supports alignments >= 2. Anything more than 2 is fine though (presuming it's a power of 2).
> I was actually thinking about that, can we assume it's a power of 2?
I believe alignments are always powers of 2. They can be 0 in IR, but then the abi alignment will be used by this point (which is 8 for these vectors, IIRC).


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D63840/new/

https://reviews.llvm.org/D63840