[PATCH] D64665: [MachinePipeliner] Refactor schedule emission logic

[Jinsong Ji via Phabricator via llvm-commits]

jsji added a comment.
Herald added a subscriber: wuzish.

Yes, good job! All the existing lit test passed.
Haven't done run time verification, but there are a few compile time assertion & abort when compiling test-suites,
I have reduced some of them and committed in https://reviews.llvm.org/rL367732 for your further investigation.



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Comment at: lib/CodeGen/MachinePipeliner.cpp:4268
+  S.PrevLC = LC;
+  return TargetRegisterInfo::isVirtualRegister(LC) ? Optional<unsigned>()
+                                                   : S.FirstLC;
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This needs to rebase to latest ToT. Using `Register::` instead.


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  https://reviews.llvm.org/D64665/new/

https://reviews.llvm.org/D64665