[llvm] r367645 - [PowerPC][Peephole] Check if `extsw`'s second operand is a virtual register

[Kai Luo via llvm-commits]

Author: lkail
Date: Thu Aug  1 20:14:17 2019
New Revision: 367645

URL: http://llvm.org/viewvc/llvm-project?rev=367645&view=rev
Log:
[PowerPC][Peephole] Check if `extsw`'s second operand is a virtual register

Summary:
When combining `extsw` and `sldi` in `PPCMIPeephole`, we have to check
if `extsw`'s second operand is a virtual register, otherwise we might
get miscompile.

Differential Revision: https://reviews.llvm.org/D65315

Modified:
    llvm/trunk/lib/Target/PowerPC/PPCMIPeephole.cpp
    llvm/trunk/test/CodeGen/MIR/PowerPC/peephole-miscompile-extswsli.mir

Modified: llvm/trunk/lib/Target/PowerPC/PPCMIPeephole.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCMIPeephole.cpp?rev=367645&r1=367644&r2=367645&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCMIPeephole.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCMIPeephole.cpp Thu Aug  1 20:14:17 2019
@@ -1426,6 +1426,12 @@ bool PPCMIPeephole::combineSEXTAndSHL(Ma
   if (!MRI->hasOneNonDBGUse(SrcReg))
     return false;
 
+  assert(SrcMI->getNumOperands() == 2 && "EXTSW should have 2 operands");
+  assert(SrcMI->getOperand(1).isReg() &&
+         "EXTSW's second operand should be a register");
+  if (!Register::isVirtualRegister(SrcMI->getOperand(1).getReg()))
+    return false;
+
   LLVM_DEBUG(dbgs() << "Combining pair: ");
   LLVM_DEBUG(SrcMI->dump());
   LLVM_DEBUG(MI.dump());

Modified: llvm/trunk/test/CodeGen/MIR/PowerPC/peephole-miscompile-extswsli.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/PowerPC/peephole-miscompile-extswsli.mir?rev=367645&r1=367644&r2=367645&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/MIR/PowerPC/peephole-miscompile-extswsli.mir (original)
+++ llvm/trunk/test/CodeGen/MIR/PowerPC/peephole-miscompile-extswsli.mir Thu Aug  1 20:14:17 2019
@@ -20,10 +20,11 @@ body:             |
   ; CHECK:   B %bb.1
   ; CHECK: bb.1:
   ; CHECK:   liveins: $x3
+  ; CHECK:   [[EXTSW:%[0-9]+]]:g8rc = EXTSW $x3
   ; CHECK:   [[RLDICR:%[0-9]+]]:g8rc = RLDICR [[ANDIo8_]], 2, 61
   ; CHECK:   $x3 = COPY [[RLDICR]]
-  ; CHECK:   [[EXTSWSLI:%[0-9]+]]:g8rc = EXTSWSLI $x3, 2, implicit-def $carry
-  ; CHECK:   [[ADD8_:%[0-9]+]]:g8rc = ADD8 [[COPY3]], [[EXTSWSLI]]
+  ; CHECK:   [[RLDICR1:%[0-9]+]]:g8rc = RLDICR [[EXTSW]], 2, 61
+  ; CHECK:   [[ADD8_:%[0-9]+]]:g8rc = ADD8 [[COPY3]], [[RLDICR1]]
   ; CHECK:   $x3 = COPY [[ADD8_]]
   ; CHECK:   BLR8 implicit $lr8, implicit $rm, implicit $x3
   ; CHECK: bb.2: