[PATCH] D65497: [RISCV] Avoid generating AssertZext for RV64 when lowering floating Libcall

[Shiva Chen via Phabricator via llvm-commits]

shiva0217 updated this revision to Diff 212952.
shiva0217 added a comment.

Update the patch to catch divsf3 case.


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D65497/new/

https://reviews.llvm.org/D65497

Files:
  include/llvm/CodeGen/TargetLowering.h
  lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
  lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  lib/CodeGen/SelectionDAG/TargetLowering.cpp
  lib/Target/RISCV/RISCVISelLowering.cpp
  lib/Target/RISCV/RISCVISelLowering.h
  test/CodeGen/RISCV/rv32i-rv64i-float-double.ll
  test/CodeGen/RISCV/rv64-complex-float.ll

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