[PATCH] D65607: [DAGCombiner] try to convert opposing shifts to casts

[Sanjay Patel via Phabricator via llvm-commits]

spatel created this revision.
spatel added reviewers: xbolva00, lebedev.ri, craig.topper, RKSimon.
Herald added subscribers: hiraditya, javed.absar, mcrosier.
Herald added a project: LLVM.

This reverses a questionable IR canonicalization when a truncate is free:

  sra (add (shl X, N1C), AddC), N1C -->
  sext (add (trunc X to (width - N1C)), AddC')

https://rise4fun.com/Alive/slRC

More details in PR42644:
https://bugs.llvm.org/show_bug.cgi?id=42644

I limited this to pre-legalization for code simplicity because that should be enough to reverse the IR patterns. I don't have any evidence (no regression test diffs) that we need to try this later.


https://reviews.llvm.org/D65607

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/AArch64/shift-mod.ll
  llvm/test/CodeGen/X86/shift-combine.ll

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