[llvm] r367540 - [AArch64] Do not allocate unnecessary emergency slot.

[Sander de Smalen via llvm-commits]

Author: s.desmalen
Date: Thu Aug  1 03:53:45 2019
New Revision: 367540

URL: http://llvm.org/viewvc/llvm-project?rev=367540&view=rev
Log:
[AArch64] Do not allocate unnecessary emergency slot.

Fix an issue where the compiler still allocates an emergency spill slot even
though it already decided to spill an extra callee-save register to use
as a scratch register.

Reviewers: gberry, thegameg, mstorsjo, t.p.northover

Reviewed By: thegameg

Differential Revision: https://reviews.llvm.org/D65504

Added:
    llvm/trunk/test/CodeGen/AArch64/extra-callee-save.mir
Modified:
    llvm/trunk/lib/Target/AArch64/AArch64FrameLowering.cpp

Modified: llvm/trunk/lib/Target/AArch64/AArch64FrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64FrameLowering.cpp?rev=367540&r1=367539&r2=367540&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64FrameLowering.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64FrameLowering.cpp Thu Aug  1 03:53:45 2019
@@ -2113,7 +2113,7 @@ void AArch64FrameLowering::determineCall
     SavedRegs.set(AArch64::LR);
   }
 
-  LLVM_DEBUG(dbgs() << "*** determineCalleeSaves\nUsed CSRs:";
+  LLVM_DEBUG(dbgs() << "*** determineCalleeSaves\nSaved CSRs:";
              for (unsigned Reg
                   : SavedRegs.set_bits()) dbgs()
              << ' ' << printReg(Reg, RegInfo);
@@ -2145,7 +2145,7 @@ void AArch64FrameLowering::determineCall
       // store the pair.
       if (produceCompactUnwindFrame(MF))
         SavedRegs.set(UnspilledCSGPRPaired);
-      ExtraCSSpill = UnspilledCSGPRPaired;
+      ExtraCSSpill = UnspilledCSGPR;
     }
 
     // If we didn't find an extra callee-saved register to spill, create

Added: llvm/trunk/test/CodeGen/AArch64/extra-callee-save.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/extra-callee-save.mir?rev=367540&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/extra-callee-save.mir (added)
+++ llvm/trunk/test/CodeGen/AArch64/extra-callee-save.mir Thu Aug  1 03:53:45 2019
@@ -0,0 +1,28 @@
+#RUN: llc -mtriple=aarch64-- -run-pass prologepilog %s -o - | FileCheck %s
+# Check that we spill a scratch register, but not also an additional
+# emergency spill slot.
+---
+name: big_stack
+# CHECK-LABEL: name: big_stack
+# CHECK: frame-setup STPXi killed $x20, killed $x19
+# CHECK: $sp = frame-setup SUBXri $sp, 8, 12
+# CHECK-NOT: frame-setup SUBXri $sp, 16, 0
+tracksRegLiveness: true
+stack:
+  - { id: 0, name: '', size: 32761, alignment: 8 }
+body: |
+  bb.0:
+    $x19 = IMPLICIT_DEF
+  ; $x20 can be used as scratch register.
+    $x21 = IMPLICIT_DEF
+    $x22 = IMPLICIT_DEF
+    $x23 = IMPLICIT_DEF
+    $x24 = IMPLICIT_DEF
+    $x25 = IMPLICIT_DEF
+    $x26 = IMPLICIT_DEF
+    $x27 = IMPLICIT_DEF
+    $x28 = IMPLICIT_DEF
+    $lr  = IMPLICIT_DEF
+    $fp  = IMPLICIT_DEF
+    RET_ReallyLR
+...