[PATCH] D65354: [X86] Let MachineCombiner reassociate adds for ILP

[Philip Reames via Phabricator via llvm-commits]

reames added a comment.

In D65354#1606210 <https://reviews.llvm.org/D65354#1606210>, @spatel wrote:

> IIRC, MachineCombiner has the potential to cause spills (it runs without real knowledge of register pressure)...and if we spill, then we have likely killed all hope for a perf improvement due to better throughput of math/logic. This is true for any reassociable opcode, but x86 scalar 'add' has more potential chance for trouble due to prevalence and so few available registers ( (as seen by the number of diffs here?).
>
> So it's correct that there was no principled reason to leave 'add' out, but the practical concern was spilling. I have not looked at the test diffs here, but if there's evidence of extra instructions, then we're probably going to see perf regressions rather than improvements?


I hear the concern here, but not reassociating on adds also means we miss some semi major performance opportunities.  Any suggestions on how to break the impasse with a tractable amount of work?  As in, any suggestions on how to implement a reasonable register pressure heuristic in MachineCombiner?


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