[llvm] r367096 - [TargetLowering] SimplifyMultipleUseDemandedBits - add SIGN_EXTEND_INREG support.

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Fri Jul 26 02:41:08 2019
New Revision: 367096

URL: http://llvm.org/viewvc/llvm-project?rev=367096&view=rev
Log:
[TargetLowering] SimplifyMultipleUseDemandedBits - add SIGN_EXTEND_INREG support.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
    llvm/trunk/test/CodeGen/AArch64/srem-seteq.ll
    llvm/trunk/test/CodeGen/ARM/ParallelDSP/multi-use-loads.ll

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=367096&r1=367095&r2=367096&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Fri Jul 26 02:41:08 2019
@@ -666,6 +666,13 @@ SDValue TargetLowering::SimplifyMultiple
       return Op.getOperand(1);
     break;
   }
+  case ISD::SIGN_EXTEND_INREG: {
+    // If none of the extended bits are demanded, eliminate the sextinreg.
+    EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
+    if (DemandedBits.getActiveBits() <= ExVT.getScalarSizeInBits())
+      return Op.getOperand(0);
+    break;
+  }
   case ISD::VECTOR_SHUFFLE: {
     ArrayRef<int> ShuffleMask = cast<ShuffleVectorSDNode>(Op)->getMask();
 

Modified: llvm/trunk/test/CodeGen/AArch64/srem-seteq.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/srem-seteq.ll?rev=367096&r1=367095&r2=367096&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/srem-seteq.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/srem-seteq.ll Fri Jul 26 02:41:08 2019
@@ -101,11 +101,11 @@ define i16 @test_srem_even(i16 %X) nounw
 ; CHECK-NEXT:    movk w9, #37449, lsl #16
 ; CHECK-NEXT:    smull x9, w8, w9
 ; CHECK-NEXT:    lsr x9, x9, #32
-; CHECK-NEXT:    add w9, w9, w8
-; CHECK-NEXT:    asr w10, w9, #3
-; CHECK-NEXT:    add w9, w10, w9, lsr #31
-; CHECK-NEXT:    mov w10, #14
-; CHECK-NEXT:    msub w8, w9, w10, w8
+; CHECK-NEXT:    add w8, w9, w8
+; CHECK-NEXT:    asr w9, w8, #3
+; CHECK-NEXT:    add w8, w9, w8, lsr #31
+; CHECK-NEXT:    mov w9, #14
+; CHECK-NEXT:    msub w8, w8, w9, w0
 ; CHECK-NEXT:    tst w8, #0xffff
 ; CHECK-NEXT:    cset w0, ne
 ; CHECK-NEXT:    ret

Modified: llvm/trunk/test/CodeGen/ARM/ParallelDSP/multi-use-loads.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/ParallelDSP/multi-use-loads.ll?rev=367096&r1=367095&r2=367096&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/ParallelDSP/multi-use-loads.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/ParallelDSP/multi-use-loads.ll Fri Jul 26 02:41:08 2019
@@ -418,8 +418,8 @@ for.body:
 define i32 @multi_uses(i32 %arg, i32* nocapture readnone %arg1, i16* nocapture readonly %arg2, i16* nocapture readonly %arg3) {
 ; CHECK-LE-LABEL: multi_uses:
 ; CHECK-LE:       @ %bb.0: @ %entry
-; CHECK-LE-NEXT:    .save {r4, r5, r7, lr}
-; CHECK-LE-NEXT:    push {r4, r5, r7, lr}
+; CHECK-LE-NEXT:    .save {r4, lr}
+; CHECK-LE-NEXT:    push {r4, lr}
 ; CHECK-LE-NEXT:    cmp r0, #1
 ; CHECK-LE-NEXT:    blt .LBB4_4
 ; CHECK-LE-NEXT:  @ %bb.1: @ %for.body.preheader
@@ -432,21 +432,20 @@ define i32 @multi_uses(i32 %arg, i32* no
 ; CHECK-LE-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; CHECK-LE-NEXT:    ldr r1, [r3, #2]!
 ; CHECK-LE-NEXT:    ldr r4, [r2, #2]!
-; CHECK-LE-NEXT:    sxth r5, r1
-; CHECK-LE-NEXT:    smlad lr, r4, r1, lr
-; CHECK-LE-NEXT:    eor.w r1, r5, r12
-; CHECK-LE-NEXT:    muls r1, r5, r1
 ; CHECK-LE-NEXT:    subs r0, #1
+; CHECK-LE-NEXT:    smlad lr, r4, r1, lr
+; CHECK-LE-NEXT:    eor.w r4, r1, r12
+; CHECK-LE-NEXT:    mul r1, r4, r1
 ; CHECK-LE-NEXT:    lsl.w r12, r1, #16
 ; CHECK-LE-NEXT:    bne .LBB4_2
 ; CHECK-LE-NEXT:  @ %bb.3: @ %for.cond.cleanup
 ; CHECK-LE-NEXT:    add.w r0, lr, r12
-; CHECK-LE-NEXT:    pop {r4, r5, r7, pc}
+; CHECK-LE-NEXT:    pop {r4, pc}
 ; CHECK-LE-NEXT:  .LBB4_4:
 ; CHECK-LE-NEXT:    mov.w lr, #0
 ; CHECK-LE-NEXT:    mov.w r12, #0
 ; CHECK-LE-NEXT:    add.w r0, lr, r12
-; CHECK-LE-NEXT:    pop {r4, r5, r7, pc}
+; CHECK-LE-NEXT:    pop {r4, pc}
 ;
 ; CHECK-BE-LABEL: multi_uses:
 ; CHECK-BE:       @ %bb.0: @ %entry