[llvm] r366922 - [SelectionDAG] makeEquivalentMemoryOrdering - early out for equal chains (PR42727)

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Wed Jul 24 09:53:14 2019
New Revision: 366922

URL: http://llvm.org/viewvc/llvm-project?rev=366922&view=rev
Log:
[SelectionDAG] makeEquivalentMemoryOrdering - early out for equal chains (PR42727)

If we are already using the same chain for the old/new memory ops then just return.

Fixes PR42727 which had getLoad() reusing an existing node.

Added:
    llvm/trunk/test/CodeGen/X86/pr42727.ll
Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=366922&r1=366921&r2=366922&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Jul 24 09:53:14 2019
@@ -8619,7 +8619,7 @@ SDValue SelectionDAG::makeEquivalentMemo
   // TokenFactor.
   SDValue OldChain = SDValue(OldLoad, 1);
   SDValue NewChain = SDValue(NewMemOp.getNode(), 1);
-  if (!OldLoad->hasAnyUseOfValue(1))
+  if (OldChain == NewChain || !OldLoad->hasAnyUseOfValue(1))
     return NewChain;
 
   SDValue TokenFactor =

Added: llvm/trunk/test/CodeGen/X86/pr42727.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr42727.ll?rev=366922&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/pr42727.ll (added)
+++ llvm/trunk/test/CodeGen/X86/pr42727.ll Wed Jul 24 09:53:14 2019
@@ -0,0 +1,34 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-w64-windows-gnu | FileCheck %s
+
+%union.c_v256.26.65.104.143.962.1248 = type { [4 x i64] }
+
+define void @_ZN14simd_test_avx216c_imm_v256_alignILi1EEE6c_v256S1_S1_(%union.c_v256.26.65.104.143.962.1248* byval(%union.c_v256.26.65.104.143.962.1248) align 4) #0 {
+; CHECK-LABEL: _ZN14simd_test_avx216c_imm_v256_alignILi1EEE6c_v256S1_S1_:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vmovdqu {{[0-9]+}}(%esp), %xmm0
+; CHECK-NEXT:    vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
+; CHECK-NEXT:    vinserti128 $1, %xmm1, %ymm0, %ymm0
+; CHECK-NEXT:    vpsllq $56, %ymm0, %ymm0
+; CHECK-NEXT:    vmovdqu %ymm0, (%eax)
+; CHECK-NEXT:    vzeroupper
+; CHECK-NEXT:    retl
+entry:
+  %b.sroa.0.sroa.2.0.b.sroa.0.0..sroa_cast.sroa_idx38 = getelementptr inbounds %union.c_v256.26.65.104.143.962.1248, %union.c_v256.26.65.104.143.962.1248* %0, i32 0, i32 0, i32 1
+  %1 = bitcast i64* %b.sroa.0.sroa.2.0.b.sroa.0.0..sroa_cast.sroa_idx38 to <2 x i64>*
+  %2 = load <2 x i64>, <2 x i64>* %1, align 4
+  %b.sroa.0.sroa.4.0.copyload = load i64, i64* undef, align 4
+  %3 = extractelement <2 x i64> %2, i32 0
+  %4 = extractelement <2 x i64> %2, i32 1
+  %5 = insertelement <4 x i64> undef, i64 %3, i32 0
+  %6 = insertelement <4 x i64> %5, i64 %4, i32 1
+  %7 = insertelement <4 x i64> %6, i64 %b.sroa.0.sroa.4.0.copyload, i32 2
+  %8 = insertelement <4 x i64> %7, i64 undef, i32 3
+  %9 = shl <4 x i64> %8, <i64 56, i64 56, i64 56, i64 56>
+  %10 = or <4 x i64> %9, zeroinitializer
+  store <4 x i64> %10, <4 x i64>* undef, align 8
+  ret void
+}
+
+attributes #0 = { "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="pentium4" "target-features"="+avx,+avx2,+cx8,+fxsr,+mmx,+popcnt,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave" "unsafe-fp-math"="false" "use-soft-float"="false" }
+