[PATCH] D65205: [RISCV] Add Custom Parser for Atomic Memory Operands

[Sam Elliott via Phabricator via llvm-commits]

lenary created this revision.
lenary added reviewers: asb, lewis-revill.
Herald added subscribers: llvm-commits, Jim, benna, psnobl, jocewei, PkmX, jfb, rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, MaskRay, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, apazos, simoncook, johnrusso, rbar, hiraditya.
Herald added a project: LLVM.
lenary added a child revision: D54296: [RISCV] Lower inline asm constraint A for RISC-V.

GCC Accepts both (reg) and 0(reg) for atomic instruction memory
operands. These instructions do not allow for an offset in their
encoding, so in the latter case, the 0 is silently dropped.

Due to how we have structured the RISCVAsmParser, the easiest way to add
support for parsing this offset is to add a custom AsmOperand and
parser. This parser drops all the parens, and just keeps the register.

This commit also adds a custom printer for these operands, which matches
the GCC canonical printer, printing both `(a0)` and `0(a0)` as `(a0)`.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D65205

Files:
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h
  llvm/lib/Target/RISCV/RISCVInstrInfoA.td
  llvm/test/MC/RISCV/rv32a-invalid.s
  llvm/test/MC/RISCV/rv64a-aliases-valid.s
  llvm/test/MC/RISCV/rv64a-invalid.s
  llvm/test/MC/RISCV/rva-aliases-invalid.s
  llvm/test/MC/RISCV/rva-aliases-valid.s

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