[PATCH] D65145: [AArch64][SVE] Allow explicit size specifier for predicate operand

[Momchil Velikov via Phabricator via llvm-commits]

chill created this revision.
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... for the vector forms of `{SQ,UQ,}{INC,DEC}P` instructions. Also continue
supporting the existing behaviour of not requiring an explicit size
specifier. The preferred disassembly is *with* the specifier.

This is implemented by redefining instruction forms to require vector predicates
with explicit size and adding aliases, which allow a predicate with no size.


https://reviews.llvm.org/D65145

Files:
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/test/MC/AArch64/SVE/decp.s
  llvm/test/MC/AArch64/SVE/incp.s
  llvm/test/MC/AArch64/SVE/sqdecp.s
  llvm/test/MC/AArch64/SVE/sqincp.s
  llvm/test/MC/AArch64/SVE/uqdecp.s
  llvm/test/MC/AArch64/SVE/uqincp.s

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