[PATCH] D64726: AMDGPU/GlobalISel: Fix not constraining result reg of copies to VCC

[Nicolai Hähnle via Phabricator via llvm-commits]

nhaehnle added a comment.

Okay, the possibility of an AssertZext is an interesting point. So let me try the other way around: What would the MIR at this stage look like to enforce an `and`?

In the sample IR I had it was the `G_ZEXT` which became an `and`, but a `G_ZEXT` to copy from `sgpr(s1)` to `vcc(s1)` doesn't really make sense since both are s1...

To make this more concrete, the GlobalISel path currently generates incorrect code for:

  define amdgpu_ps float @foo(i32 inreg %a, i32 %b, i32 %c) {
    %cc = trunc i32 %a to i1
    %r = select i1 %cc, i32 %b, i32 %c
    %r.f = bitcast i32 %r to float
    ret float %r.f
  }

The non-GlobalISel path does the right thing (though I wonder whether it might be able to use scc instead of vcc, but that can be a separate discussion).


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D64726/new/

https://reviews.llvm.org/D64726