[PATCH] D65052: [ARM] MVE predicate register support

[Dave Green via Phabricator via llvm-commits]

dmgreen created this revision.
dmgreen added reviewers: t.p.northover, SjoerdMeijer, samparker, simon_tatham, ostannard.
Herald added subscribers: hiraditya, kristof.beyls, javed.absar, qcolombet.
Herald added a project: LLVM.

This adds support code for building and shuffling i1 predicate registers. It generally uses two basic principles, either converting the predicate into an scalar (through a PREDICATE_CAST) and doing scalar operations on it there, or by converting the register to an full vector register and back.

Some of the code here is a not super efficient but will hopefully cover most cases of moving i1 vectors around and can be improved in subsequent patches.

Some code by David Sherwood.


https://reviews.llvm.org/D65052

Files:
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/lib/Target/ARM/ARMISelLowering.h
  llvm/lib/Target/ARM/ARMInstrMVE.td
  llvm/test/CodeGen/Thumb2/mve-pred-build-const.ll
  llvm/test/CodeGen/Thumb2/mve-pred-build-var.ll
  llvm/test/CodeGen/Thumb2/mve-pred-ext.ll
  llvm/test/CodeGen/Thumb2/mve-pred-shuffle.ll
  llvm/test/CodeGen/Thumb2/mve-pred-spill.ll
  llvm/test/CodeGen/Thumb2/mve-vcmp.ll

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