[llvm] r366564 - [NFC][InstCombine] Redundant masking before left-shift: tests with assume
Roman Lebedev via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 19 04:29:05 PDT 2019
Author: lebedevri
Date: Fri Jul 19 04:29:04 2019
New Revision: 366564
URL: http://llvm.org/viewvc/llvm-project?rev=366564&view=rev
Log:
[NFC][InstCombine] Redundant masking before left-shift: tests with assume
If the legality check is `(shiftNbits-maskNbits) s>= 0`,
then we can simplify it to `shiftNbits u>= maskNbits`,
which is easier to check for.
However, currently switching the `dropRedundantMaskingOfLeftShiftInput()`
to `SimplifyICmpInst()` does not catch these cases and regresses
currently-handled cases, so i'll leave it as is for now.
https://rise4fun.com/Alive/25P
Modified:
llvm/trunk/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-c.ll
llvm/trunk/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-d.ll
llvm/trunk/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-e.ll
llvm/trunk/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-f.ll
Modified: llvm/trunk/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-c.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-c.ll?rev=366564&r1=366563&r2=366564&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-c.ll (original)
+++ llvm/trunk/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-c.ll Fri Jul 19 04:29:04 2019
@@ -237,10 +237,36 @@ define i32 @t10_nuw_nsw(i32 %x, i32 %nbi
ret i32 %t2
}
+; Special test
+
+declare void @llvm.assume(i1 %cond)
+
+; We can't simplify (%shiftnbits-%masknbits) but we have an assumption.
+define i32 @t11_assume_uge(i32 %x, i32 %masknbits, i32 %shiftnbits) {
+; CHECK-LABEL: @t11_assume_uge(
+; CHECK-NEXT: [[CMP:%.*]] = icmp uge i32 [[SHIFTNBITS:%.*]], [[MASKNBITS:%.*]]
+; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]])
+; CHECK-NEXT: [[T0:%.*]] = lshr i32 -1, [[MASKNBITS]]
+; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[X:%.*]]
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: [[T2:%.*]] = shl i32 [[T1]], [[SHIFTNBITS]]
+; CHECK-NEXT: ret i32 [[T2]]
+;
+ %cmp = icmp uge i32 %shiftnbits, %masknbits
+ call void @llvm.assume(i1 %cmp)
+ %t0 = lshr i32 -1, %masknbits
+ %t1 = and i32 %t0, %x
+ call void @use32(i32 %t0)
+ call void @use32(i32 %t1)
+ %t2 = shl i32 %t1, %shiftnbits
+ ret i32 %t2
+}
+
; Negative tests
-define i32 @n11_not_minus_one(i32 %x, i32 %nbits) {
-; CHECK-LABEL: @n11_not_minus_one(
+define i32 @n12_not_minus_one(i32 %x, i32 %nbits) {
+; CHECK-LABEL: @n12_not_minus_one(
; CHECK-NEXT: [[T0:%.*]] = lshr i32 -2, [[NBITS:%.*]]
; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[X:%.*]]
; CHECK-NEXT: call void @use32(i32 [[T0]])
@@ -256,8 +282,8 @@ define i32 @n11_not_minus_one(i32 %x, i3
ret i32 %t2
}
-define i32 @n12_shamt_is_smaller(i32 %x, i32 %nbits) {
-; CHECK-LABEL: @n12_shamt_is_smaller(
+define i32 @n13_shamt_is_smaller(i32 %x, i32 %nbits) {
+; CHECK-LABEL: @n13_shamt_is_smaller(
; CHECK-NEXT: [[T0:%.*]] = lshr i32 -1, [[NBITS:%.*]]
; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[X:%.*]]
; CHECK-NEXT: [[T2:%.*]] = add i32 [[NBITS]], -1
Modified: llvm/trunk/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-d.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-d.ll?rev=366564&r1=366563&r2=366564&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-d.ll (original)
+++ llvm/trunk/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-d.ll Fri Jul 19 04:29:04 2019
@@ -288,10 +288,40 @@ define i32 @t10_nuw_nsw(i32 %x, i32 %nbi
ret i32 %t3
}
+; Special test
+
+declare void @llvm.assume(i1 %cond)
+
+; We can't simplify (%shiftnbits-%masknbits) but we have an assumption.
+define i32 @t11_assume_uge(i32 %x, i32 %masknbits, i32 %shiftnbits) {
+; CHECK-LABEL: @t11_assume_uge(
+; CHECK-NEXT: [[CMP:%.*]] = icmp uge i32 [[SHIFTNBITS:%.*]], [[MASKNBITS:%.*]]
+; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]])
+; CHECK-NEXT: [[T0:%.*]] = shl i32 -1, [[MASKNBITS]]
+; CHECK-NEXT: [[T1:%.*]] = lshr i32 [[T0]], [[MASKNBITS]]
+; CHECK-NEXT: [[T2:%.*]] = and i32 [[T1]], [[X:%.*]]
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: call void @use32(i32 [[T2]])
+; CHECK-NEXT: [[T4:%.*]] = shl i32 [[T2]], [[SHIFTNBITS]]
+; CHECK-NEXT: ret i32 [[T4]]
+;
+ %cmp = icmp uge i32 %shiftnbits, %masknbits
+ call void @llvm.assume(i1 %cmp)
+ %t0 = shl i32 -1, %masknbits
+ %t1 = lshr i32 %t0, %masknbits
+ %t2 = and i32 %t1, %x
+ call void @use32(i32 %t0)
+ call void @use32(i32 %t1)
+ call void @use32(i32 %t2)
+ %t4 = shl i32 %t2, %shiftnbits
+ ret i32 %t4
+}
+
; Negative tests
-define i32 @n11_different_shamts0(i32 %x, i32 %nbits0, i32 %nbits1) {
-; CHECK-LABEL: @n11_different_shamts0(
+define i32 @n12_different_shamts0(i32 %x, i32 %nbits0, i32 %nbits1) {
+; CHECK-LABEL: @n12_different_shamts0(
; CHECK-NEXT: [[T0:%.*]] = shl i32 [[X:%.*]], [[NBITS0:%.*]]
; CHECK-NEXT: [[T1:%.*]] = lshr i32 [[T0]], [[NBITS1:%.*]]
; CHECK-NEXT: [[T2:%.*]] = and i32 [[T1]], [[X]]
@@ -311,8 +341,8 @@ define i32 @n11_different_shamts0(i32 %x
ret i32 %t3
}
-define i32 @n12_different_shamts1(i32 %x, i32 %nbits0, i32 %nbits1) {
-; CHECK-LABEL: @n12_different_shamts1(
+define i32 @n13_different_shamts1(i32 %x, i32 %nbits0, i32 %nbits1) {
+; CHECK-LABEL: @n13_different_shamts1(
; CHECK-NEXT: [[T0:%.*]] = shl i32 [[X:%.*]], [[NBITS0:%.*]]
; CHECK-NEXT: [[T1:%.*]] = lshr i32 [[T0]], [[NBITS1:%.*]]
; CHECK-NEXT: [[T2:%.*]] = and i32 [[T1]], [[X]]
@@ -332,8 +362,8 @@ define i32 @n12_different_shamts1(i32 %x
ret i32 %t3
}
-define i32 @n13_shamt_is_smaller(i32 %x, i32 %nbits) {
-; CHECK-LABEL: @n13_shamt_is_smaller(
+define i32 @n14_shamt_is_smaller(i32 %x, i32 %nbits) {
+; CHECK-LABEL: @n14_shamt_is_smaller(
; CHECK-NEXT: [[T0:%.*]] = shl i32 -1, [[NBITS:%.*]]
; CHECK-NEXT: [[T1:%.*]] = lshr i32 [[T0]], [[NBITS]]
; CHECK-NEXT: [[T2:%.*]] = and i32 [[T1]], [[X:%.*]]
Modified: llvm/trunk/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-e.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-e.ll?rev=366564&r1=366563&r2=366564&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-e.ll (original)
+++ llvm/trunk/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-e.ll Fri Jul 19 04:29:04 2019
@@ -173,10 +173,36 @@ define i32 @t7_nuw_nsw(i32 %x, i32 %nbit
ret i32 %t2
}
+; Special test
+
+declare void @llvm.assume(i1 %cond)
+
+; We can't simplify (%shiftnbits-%masknbits) but we have an assumption.
+define i32 @t8_assume_uge(i32 %x, i32 %masknbits, i32 %shiftnbits) {
+; CHECK-LABEL: @t8_assume_uge(
+; CHECK-NEXT: [[CMP:%.*]] = icmp uge i32 [[SHIFTNBITS:%.*]], [[MASKNBITS:%.*]]
+; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]])
+; CHECK-NEXT: [[T0:%.*]] = shl i32 [[X:%.*]], [[MASKNBITS]]
+; CHECK-NEXT: [[T1:%.*]] = lshr i32 [[T0]], [[MASKNBITS]]
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: [[T2:%.*]] = shl i32 [[T1]], [[SHIFTNBITS]]
+; CHECK-NEXT: ret i32 [[T2]]
+;
+ %cmp = icmp uge i32 %shiftnbits, %masknbits
+ call void @llvm.assume(i1 %cmp)
+ %t0 = shl i32 %x, %masknbits
+ %t1 = lshr i32 %t0, %masknbits
+ call void @use32(i32 %t0)
+ call void @use32(i32 %t1)
+ %t2 = shl i32 %t1, %shiftnbits
+ ret i32 %t2
+}
+
; Negative tests
-define i32 @n8_different_shamts0(i32 %x, i32 %nbits0, i32 %nbits1) {
-; CHECK-LABEL: @n8_different_shamts0(
+define i32 @n9_different_shamts0(i32 %x, i32 %nbits0, i32 %nbits1) {
+; CHECK-LABEL: @n9_different_shamts0(
; CHECK-NEXT: [[T0:%.*]] = shl i32 [[X:%.*]], [[NBITS0:%.*]]
; CHECK-NEXT: [[T1:%.*]] = lshr i32 [[T0]], [[NBITS1:%.*]]
; CHECK-NEXT: call void @use32(i32 [[T0]])
@@ -192,8 +218,8 @@ define i32 @n8_different_shamts0(i32 %x,
ret i32 %t2
}
-define i32 @n9_different_shamts1(i32 %x, i32 %nbits0, i32 %nbits1) {
-; CHECK-LABEL: @n9_different_shamts1(
+define i32 @n10_different_shamts1(i32 %x, i32 %nbits0, i32 %nbits1) {
+; CHECK-LABEL: @n10_different_shamts1(
; CHECK-NEXT: [[T0:%.*]] = shl i32 [[X:%.*]], [[NBITS0:%.*]]
; CHECK-NEXT: [[T1:%.*]] = lshr i32 [[T0]], [[NBITS1:%.*]]
; CHECK-NEXT: call void @use32(i32 [[T0]])
@@ -209,8 +235,8 @@ define i32 @n9_different_shamts1(i32 %x,
ret i32 %t2
}
-define i32 @n10_shamt_is_smaller(i32 %x, i32 %nbits) {
-; CHECK-LABEL: @n10_shamt_is_smaller(
+define i32 @n11_shamt_is_smaller(i32 %x, i32 %nbits) {
+; CHECK-LABEL: @n11_shamt_is_smaller(
; CHECK-NEXT: [[T0:%.*]] = shl i32 [[X:%.*]], [[NBITS:%.*]]
; CHECK-NEXT: [[T1:%.*]] = lshr i32 [[T0]], [[NBITS]]
; CHECK-NEXT: [[T2:%.*]] = add i32 [[NBITS]], -1
Modified: llvm/trunk/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-f.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-f.ll?rev=366564&r1=366563&r2=366564&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-f.ll (original)
+++ llvm/trunk/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-f.ll Fri Jul 19 04:29:04 2019
@@ -173,10 +173,36 @@ define i32 @t7_nuw_nsw(i32 %x, i32 %nbit
ret i32 %t2
}
+; Special test
+
+declare void @llvm.assume(i1 %cond)
+
+; We can't simplify (%shiftnbits-%masknbits) but we have an assumption.
+define i32 @t8_assume_uge(i32 %x, i32 %masknbits, i32 %shiftnbits) {
+; CHECK-LABEL: @t8_assume_uge(
+; CHECK-NEXT: [[CMP:%.*]] = icmp uge i32 [[SHIFTNBITS:%.*]], [[MASKNBITS:%.*]]
+; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]])
+; CHECK-NEXT: [[T0:%.*]] = shl i32 [[X:%.*]], [[MASKNBITS]]
+; CHECK-NEXT: [[T1:%.*]] = ashr i32 [[T0]], [[MASKNBITS]]
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: [[T2:%.*]] = shl i32 [[T1]], [[SHIFTNBITS]]
+; CHECK-NEXT: ret i32 [[T2]]
+;
+ %cmp = icmp uge i32 %shiftnbits, %masknbits
+ call void @llvm.assume(i1 %cmp)
+ %t0 = shl i32 %x, %masknbits
+ %t1 = ashr i32 %t0, %masknbits
+ call void @use32(i32 %t0)
+ call void @use32(i32 %t1)
+ %t2 = shl i32 %t1, %shiftnbits
+ ret i32 %t2
+}
+
; Negative tests
-define i32 @n8_different_shamts0(i32 %x, i32 %nbits0, i32 %nbits1) {
-; CHECK-LABEL: @n8_different_shamts0(
+define i32 @n9_different_shamts0(i32 %x, i32 %nbits0, i32 %nbits1) {
+; CHECK-LABEL: @n9_different_shamts0(
; CHECK-NEXT: [[T0:%.*]] = shl i32 [[X:%.*]], [[NBITS0:%.*]]
; CHECK-NEXT: [[T1:%.*]] = ashr i32 [[T0]], [[NBITS1:%.*]]
; CHECK-NEXT: call void @use32(i32 [[T0]])
@@ -192,8 +218,8 @@ define i32 @n8_different_shamts0(i32 %x,
ret i32 %t2
}
-define i32 @n9_different_shamts1(i32 %x, i32 %nbits0, i32 %nbits1) {
-; CHECK-LABEL: @n9_different_shamts1(
+define i32 @n10_different_shamts1(i32 %x, i32 %nbits0, i32 %nbits1) {
+; CHECK-LABEL: @n10_different_shamts1(
; CHECK-NEXT: [[T0:%.*]] = shl i32 [[X:%.*]], [[NBITS0:%.*]]
; CHECK-NEXT: [[T1:%.*]] = ashr i32 [[T0]], [[NBITS1:%.*]]
; CHECK-NEXT: call void @use32(i32 [[T0]])
@@ -209,8 +235,8 @@ define i32 @n9_different_shamts1(i32 %x,
ret i32 %t2
}
-define i32 @n10_shamt_is_smaller(i32 %x, i32 %nbits) {
-; CHECK-LABEL: @n10_shamt_is_smaller(
+define i32 @n11_shamt_is_smaller(i32 %x, i32 %nbits) {
+; CHECK-LABEL: @n11_shamt_is_smaller(
; CHECK-NEXT: [[T0:%.*]] = shl i32 [[X:%.*]], [[NBITS:%.*]]
; CHECK-NEXT: [[T1:%.*]] = ashr i32 [[T0]], [[NBITS]]
; CHECK-NEXT: [[T2:%.*]] = add i32 [[NBITS]], -1
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