[PATCH] D64960: [PowerPC] Expand v1i128 smin

[Roland Froese via Phabricator via llvm-commits]

RolandF created this revision.
RolandF added a reviewer: nemanjai.
Herald added subscribers: shchenz, wuzish, jsji, MaskRay, kbarton, hiraditya.
Herald added a project: LLVM.

Fix a regression from D60160 <https://reviews.llvm.org/D60160> where the cost model change enabled vector code to be generated with a v1i128 smin.  There isn't an instruction for that but it was marked legal in PPCISelLowering.cpp.


https://reviews.llvm.org/D64960

Files:
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/vec-min-max.ll


Index: llvm/test/CodeGen/PowerPC/vec-min-max.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/vec-min-max.ll
+++ llvm/test/CodeGen/PowerPC/vec-min-max.ll
@@ -237,3 +237,15 @@
   ret <2 x double> %1
 }
 
+define i128 @invalidv1i128(<2 x i128> %v1, <2 x i128> %v2) {
+; CHECK-LABEL: invalidv1i128:
+; CHECK-LABEL: %bb.1:
+; CHECK-NEXT: vmr
+; NOP8VEC-LABEL: invalidv1i128:
+; NOP8VEC: isel
+; NOP8VEC: isel
+%1 = icmp slt <2 x i128> %v1, %v2
+%2 = select <2 x i1> %1, <2 x i128> %v1, <2 x i128> %v2
+%3 = extractelement <2 x i128> %2, i32 0
+ret i128 %3
+}
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -560,10 +560,18 @@
 
       // For v2i64, these are only valid with P8Vector. This is corrected after
       // the loop.
-      setOperationAction(ISD::SMAX, VT, Legal);
-      setOperationAction(ISD::SMIN, VT, Legal);
-      setOperationAction(ISD::UMAX, VT, Legal);
-      setOperationAction(ISD::UMIN, VT, Legal);
+      if (VT.getSizeInBits() <= 128 && VT.getScalarSizeInBits() <= 64) {
+        setOperationAction(ISD::SMAX, VT, Legal);
+        setOperationAction(ISD::SMIN, VT, Legal);
+        setOperationAction(ISD::UMAX, VT, Legal);
+        setOperationAction(ISD::UMIN, VT, Legal);
+      }
+      else {
+        setOperationAction(ISD::SMAX, VT, Expand);
+        setOperationAction(ISD::SMIN, VT, Expand);
+        setOperationAction(ISD::UMAX, VT, Expand);
+        setOperationAction(ISD::UMIN, VT, Expand);
+      }
 
       if (Subtarget.hasVSX()) {
         setOperationAction(ISD::FMAXNUM, VT, Legal);


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