[PATCH] D64726: AMDGPU/GlobalISel: Fix not constraining result reg of copies to VCC

[Nicolai Hähnle via Phabricator via llvm-commits]

nhaehnle added a comment.

But then following this logic, I still think that by analogy with G_ZEXT, the operation of `COPY from s1 into vcc` should have the semantics of ignoring the high bits of the "s1 which is really an s32". Since there's nothing in the MIR test which guarantees that the incoming high bits of $sgpr0 are 0, the resulting code needs to have some form of masking.

(As an aside, there's an argument to be made that the resulting code should really be an S_AND_B32 with 1 followed by an S_CSELECT_B64 writing to vcc instead of using the VALU, but we should probably clear up the semantics/correctness question first.)


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  https://reviews.llvm.org/D64726/new/

https://reviews.llvm.org/D64726