[llvm] r366355 - Revert [AArch64] Add support for Transactional Memory Extension (TME)
Momchil Velikov via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 17 11:23:01 PDT 2019
Sorry, I'll keep than in mind for the future.
The one of the added tests (tme-tcancel.c) breaks bots with expensive checking enabled.
Perhaps the checker is incorrect, but regardless of it, maybe the tcancel intrinsic/instruction should not be noreturn/isBrarrier, respectively.
________________________________
From: Philip Reames <listmail at philipreames.com>
Sent: 17 July 2019 19:07:24
To: Momchil Velikov; llvm-commits at lists.llvm.org
Subject: Re: [llvm] r366355 - Revert [AArch64] Add support for Transactional Memory Extension (TME)
Reminder: Please say *why* something is being reverted.
On 7/17/19 10:43 AM, Momchil Velikov via llvm-commits wrote:
> Author: chill
> Date: Wed Jul 17 10:43:32 2019
> New Revision: 366355
>
> URL: http://llvm.org/viewvc/llvm-project?rev=366355&view=rev
> Log:
> Revert [AArch64] Add support for Transactional Memory Extension (TME)
>
> This reverts r366322 (git commit 4b8da3a503e434ddbc08ecf66582475765f449bc)
>
> Removed:
> llvm/trunk/test/CodeGen/AArch64/tme-tcancel.ll
> llvm/trunk/test/CodeGen/AArch64/tme-tcommit.ll
> llvm/trunk/test/CodeGen/AArch64/tme-tstart.ll
> llvm/trunk/test/CodeGen/AArch64/tme-ttest.ll
> llvm/trunk/test/MC/AArch64/tme-error.s
> llvm/trunk/test/MC/AArch64/tme.s
> llvm/trunk/test/MC/Disassembler/AArch64/tme.txt
> Modified:
> llvm/trunk/include/llvm/IR/IntrinsicsAArch64.td
> llvm/trunk/include/llvm/Support/AArch64TargetParser.def
> llvm/trunk/include/llvm/Support/AArch64TargetParser.h
> llvm/trunk/lib/Target/AArch64/AArch64.td
> llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td
> llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td
> llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h
> llvm/trunk/unittests/Support/TargetParserTest.cpp
>
> Modified: llvm/trunk/include/llvm/IR/IntrinsicsAArch64.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/IntrinsicsAArch64.td?rev=366355&r1=366354&r2=366355&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/IR/IntrinsicsAArch64.td (original)
> +++ llvm/trunk/include/llvm/IR/IntrinsicsAArch64.td Wed Jul 17 10:43:32 2019
> @@ -703,20 +703,3 @@ def int_aarch64_stg : Intrinsic<[], [l
> def int_aarch64_subp : Intrinsic<[llvm_i64_ty], [llvm_ptr_ty, llvm_ptr_ty],
> [IntrNoMem]>;
> }
> -
> -// Transactional Memory Extension (TME) Intrinsics
> -let TargetPrefix = "aarch64" in {
> -def int_aarch64_tstart : GCCBuiltin<"__builtin_arm_tstart">,
> - Intrinsic<[llvm_i64_ty]>;
> -
> -def int_aarch64_tcommit : GCCBuiltin<"__builtin_arm_tcommit">, Intrinsic<[]>;
> -
> -def int_aarch64_tcancel : GCCBuiltin<"__builtin_arm_tcancel">,
> - Intrinsic<[], [llvm_i64_ty],
> - [ImmArg<0>, IntrNoMem, IntrHasSideEffects,
> - IntrNoReturn]>;
> -
> -def int_aarch64_ttest : GCCBuiltin<"__builtin_arm_ttest">,
> - Intrinsic<[llvm_i64_ty], [],
> - [IntrNoMem, IntrHasSideEffects]>;
> -}
>
> Modified: llvm/trunk/include/llvm/Support/AArch64TargetParser.def
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/AArch64TargetParser.def?rev=366355&r1=366354&r2=366355&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/Support/AArch64TargetParser.def (original)
> +++ llvm/trunk/include/llvm/Support/AArch64TargetParser.def Wed Jul 17 10:43:32 2019
> @@ -79,7 +79,6 @@ AARCH64_ARCH_EXT_NAME("memtag", AArch
> AARCH64_ARCH_EXT_NAME("ssbs", AArch64::AEK_SSBS, "+ssbs", "-ssbs")
> AARCH64_ARCH_EXT_NAME("sb", AArch64::AEK_SB, "+sb", "-sb")
> AARCH64_ARCH_EXT_NAME("predres", AArch64::AEK_PREDRES, "+predres", "-predres")
> -AARCH64_ARCH_EXT_NAME("tme", AArch64::AEK_TME, "+tme", "-tme")
> #undef AARCH64_ARCH_EXT_NAME
>
> #ifndef AARCH64_CPU_NAME
>
> Modified: llvm/trunk/include/llvm/Support/AArch64TargetParser.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/AArch64TargetParser.h?rev=366355&r1=366354&r2=366355&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/Support/AArch64TargetParser.h (original)
> +++ llvm/trunk/include/llvm/Support/AArch64TargetParser.h Wed Jul 17 10:43:32 2019
> @@ -54,7 +54,6 @@ enum ArchExtKind : unsigned {
> AEK_SVE2SM4 = 1 << 25,
> AEK_SVE2SHA3 = 1 << 26,
> AEK_BITPERM = 1 << 27,
> - AEK_TME = 1 << 28,
> };
>
> enum class ArchKind {
>
> Modified: llvm/trunk/lib/Target/AArch64/AArch64.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64.td?rev=366355&r1=366354&r2=366355&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/AArch64.td (original)
> +++ llvm/trunk/lib/Target/AArch64/AArch64.td Wed Jul 17 10:43:32 2019
> @@ -345,9 +345,6 @@ def FeatureRandGen : SubtargetFeature<"r
> def FeatureMTE : SubtargetFeature<"mte", "HasMTE",
> "true", "Enable Memory Tagging Extension" >;
>
> -def FeatureTME : SubtargetFeature<"tme", "HasTME",
> - "true", "Enable Transactional Memory Extension" >;
> -
> //===----------------------------------------------------------------------===//
> // Architectures.
> //
>
> Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td?rev=366355&r1=366354&r2=366355&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td (original)
> +++ llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td Wed Jul 17 10:43:32 2019
> @@ -714,15 +714,12 @@ def logical_imm64_not : Operand<i64> {
> let ParserMatchClass = LogicalImm64NotOperand;
> }
>
> -// iXX_imm0_65535 predicates - True if the immediate is in the range [0,65535].
> -let ParserMatchClass = AsmImmRange<0, 65535>, PrintMethod = "printImmHex" in {
> -def i32_imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
> +// imm0_65535 predicate - True if the immediate is in the range [0,65535].
> +def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
> return ((uint32_t)Imm) < 65536;
> -}]>;
> -
> -def i64_imm0_65535 : Operand<i64>, ImmLeaf<i64, [{
> - return ((uint64_t)Imm) < 65536;
> -}]>;
> +}]> {
> + let ParserMatchClass = AsmImmRange<0, 65535>;
> + let PrintMethod = "printImmHex";
> }
>
> // imm0_255 predicate - True if the immediate is in the range [0,255].
> @@ -1085,46 +1082,6 @@ class RtSystemI<bit L, dag oops, dag iop
> let Inst{4-0} = Rt;
> }
>
> -// System instructions for transactional memory extension
> -class TMBaseSystemI<bit L, bits<4> CRm, bits<3> op2, dag oops, dag iops,
> - string asm, string operands, list<dag> pattern>
> - : BaseSystemI<L, oops, iops, asm, operands, pattern>,
> - Sched<[WriteSys]> {
> - let Inst{20-12} = 0b000110011;
> - let Inst{11-8} = CRm;
> - let Inst{7-5} = op2;
> - let DecoderMethod = "";
> -
> - let mayLoad = 1;
> - let mayStore = 1;
> -}
> -
> -// System instructions for transactional memory - single input operand
> -class TMSystemI<bits<4> CRm, string asm, list<dag> pattern>
> - : TMBaseSystemI<0b1, CRm, 0b011,
> - (outs GPR64:$Rt), (ins), asm, "\t$Rt", pattern> {
> - bits<5> Rt;
> - let Inst{4-0} = Rt;
> -}
> -
> -// System instructions for transactional memory - no operand
> -class TMSystemINoOperand<bits<4> CRm, string asm, list<dag> pattern>
> - : TMBaseSystemI<0b0, CRm, 0b011, (outs), (ins), asm, "", pattern> {
> - let Inst{4-0} = 0b11111;
> -}
> -
> -// System instructions for exit from transactions
> -let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
> -class TMSystemException<bits<3> op1, string asm, list<dag> pattern>
> - : I<(outs), (ins i64_imm0_65535:$imm), asm, "\t$imm", "", pattern>,
> - Sched<[WriteSys]> {
> - bits<16> imm;
> - let Inst{31-24} = 0b11010100;
> - let Inst{23-21} = op1;
> - let Inst{20-5} = imm;
> - let Inst{4-0} = 0b00000;
> -}
> -
> // Hint instructions that take both a CRm and a 3-bit immediate.
> // NOTE: ideally, this would have mayStore = 0, mayLoad = 0, but we cannot
> // model patterns with sufficiently fine granularity
> @@ -4129,7 +4086,7 @@ multiclass MemTagStore<bits<2> opc1, str
>
> let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
> class ExceptionGeneration<bits<3> op1, bits<2> ll, string asm>
> - : I<(outs), (ins i32_imm0_65535:$imm), asm, "\t$imm", "", []>,
> + : I<(outs), (ins imm0_65535:$imm), asm, "\t$imm", "", []>,
> Sched<[WriteSys]> {
> bits<16> imm;
> let Inst{31-24} = 0b11010100;
>
> Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td?rev=366355&r1=366354&r2=366355&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td (original)
> +++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td Wed Jul 17 10:43:32 2019
> @@ -133,8 +133,6 @@ def HasBTI : Predicate<"Subtar
> AssemblerPredicate<"FeatureBranchTargetId", "bti">;
> def HasMTE : Predicate<"Subtarget->hasMTE()">,
> AssemblerPredicate<"FeatureMTE", "mte">;
> -def HasTME : Predicate<"Subtarget->hasTME()">,
> - AssemblerPredicate<"FeatureTME", "tme">;
> def IsLE : Predicate<"Subtarget->isLittleEndian()">;
> def IsBE : Predicate<"!Subtarget->isLittleEndian()">;
> def IsWindows : Predicate<"Subtarget->isTargetWindows()">;
> @@ -800,21 +798,6 @@ def : InstAlias<"sys $op1, $Cn, $Cm, $op
> (SYSxt imm0_7:$op1, sys_cr_op:$Cn,
> sys_cr_op:$Cm, imm0_7:$op2, XZR)>;
>
> -
> -let Predicates = [HasTME] in {
> -
> -def TSTART : TMSystemI<0b0000, "tstart", [(set GPR64:$Rt, (int_aarch64_tstart))]>;
> -
> -def TCOMMIT : TMSystemINoOperand<0b0000, "tcommit", [(int_aarch64_tcommit)]>;
> -
> -let mayLoad = 0, mayStore = 0 in {
> -def TTEST : TMSystemI<0b0001, "ttest", [(set GPR64:$Rt, (int_aarch64_ttest))]>;
> -def TCANCEL : TMSystemException<0b011, "tcancel", [(int_aarch64_tcancel i64_imm0_65535:$imm)]> {
> - let isBarrier = 1;
> -}
> -}
> -} // HasTME
> -
> //===----------------------------------------------------------------------===//
> // Move immediate instructions.
> //===----------------------------------------------------------------------===//
> @@ -826,12 +809,12 @@ let PostEncoderMethod = "fixMOVZ" in
> defm MOVZ : MoveImmediate<0b10, "movz">;
>
> // First group of aliases covers an implicit "lsl #0".
> -def : InstAlias<"movk $dst, $imm", (MOVKWi GPR32:$dst, i32_imm0_65535:$imm, 0), 0>;
> -def : InstAlias<"movk $dst, $imm", (MOVKXi GPR64:$dst, i32_imm0_65535:$imm, 0), 0>;
> -def : InstAlias<"movn $dst, $imm", (MOVNWi GPR32:$dst, i32_imm0_65535:$imm, 0)>;
> -def : InstAlias<"movn $dst, $imm", (MOVNXi GPR64:$dst, i32_imm0_65535:$imm, 0)>;
> -def : InstAlias<"movz $dst, $imm", (MOVZWi GPR32:$dst, i32_imm0_65535:$imm, 0)>;
> -def : InstAlias<"movz $dst, $imm", (MOVZXi GPR64:$dst, i32_imm0_65535:$imm, 0)>;
> +def : InstAlias<"movk $dst, $imm", (MOVKWi GPR32:$dst, imm0_65535:$imm, 0), 0>;
> +def : InstAlias<"movk $dst, $imm", (MOVKXi GPR64:$dst, imm0_65535:$imm, 0), 0>;
> +def : InstAlias<"movn $dst, $imm", (MOVNWi GPR32:$dst, imm0_65535:$imm, 0)>;
> +def : InstAlias<"movn $dst, $imm", (MOVNXi GPR64:$dst, imm0_65535:$imm, 0)>;
> +def : InstAlias<"movz $dst, $imm", (MOVZWi GPR32:$dst, imm0_65535:$imm, 0)>;
> +def : InstAlias<"movz $dst, $imm", (MOVZXi GPR64:$dst, imm0_65535:$imm, 0)>;
>
> // Next, we have various ELF relocations with the ":XYZ_g0:sym" syntax.
> def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>;
>
> Modified: llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h?rev=366355&r1=366354&r2=366355&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h (original)
> +++ llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h Wed Jul 17 10:43:32 2019
> @@ -134,7 +134,6 @@ protected:
> bool HasBTI = false;
> bool HasRandGen = false;
> bool HasMTE = false;
> - bool HasTME = false;
>
> // Arm SVE2 extensions
> bool HasSVE2AES = false;
> @@ -381,7 +380,6 @@ public:
> bool hasBTI() const { return HasBTI; }
> bool hasRandGen() const { return HasRandGen; }
> bool hasMTE() const { return HasMTE; }
> - bool hasTME() const { return HasTME; }
> // Arm SVE2 extensions
> bool hasSVE2AES() const { return HasSVE2AES; }
> bool hasSVE2SM4() const { return HasSVE2SM4; }
>
> Removed: llvm/trunk/test/CodeGen/AArch64/tme-tcancel.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/tme-tcancel.ll?rev=366354&view=auto
> ==============================================================================
> --- llvm/trunk/test/CodeGen/AArch64/tme-tcancel.ll (original)
> +++ llvm/trunk/test/CodeGen/AArch64/tme-tcancel.ll (removed)
> @@ -1,16 +0,0 @@
> -; RUN: llc %s -o - | FileCheck %s
> -
> -target triple = "aarch64-unknown-unknown-eabi"
> -
> -define void @test_tcancel() #0 {
> - tail call void @llvm.aarch64.tcancel(i64 0) #1
> - unreachable
> -}
> -
> -declare void @llvm.aarch64.tcancel(i64 immarg) #1
> -
> -attributes #0 = { "target-features"="+tme" }
> -attributes #1 = { nounwind noreturn }
> -
> -; CHECK-LABEL: test_tcancel
> -; CHECK: tcancel
>
> Removed: llvm/trunk/test/CodeGen/AArch64/tme-tcommit.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/tme-tcommit.ll?rev=366354&view=auto
> ==============================================================================
> --- llvm/trunk/test/CodeGen/AArch64/tme-tcommit.ll (original)
> +++ llvm/trunk/test/CodeGen/AArch64/tme-tcommit.ll (removed)
> @@ -1,16 +0,0 @@
> -; RUN: llc %s -o - | FileCheck %s
> -
> -target triple = "aarch64-unknown-unknown-eabi"
> -
> -define void @test_tcommit() #0 {
> - tail call void @llvm.aarch64.tcommit()
> - ret void
> -}
> -
> -declare void @llvm.aarch64.tcommit() #1
> -
> -attributes #0 = { "target-features"="+tme" }
> -attributes #1 = { nounwind }
> -
> -; CHECK-LABEL: test_tcommit
> -; CHECK: tcommit
>
> Removed: llvm/trunk/test/CodeGen/AArch64/tme-tstart.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/tme-tstart.ll?rev=366354&view=auto
> ==============================================================================
> --- llvm/trunk/test/CodeGen/AArch64/tme-tstart.ll (original)
> +++ llvm/trunk/test/CodeGen/AArch64/tme-tstart.ll (removed)
> @@ -1,16 +0,0 @@
> -; RUN: llc %s -o - | FileCheck %s
> -
> -target triple = "aarch64-unknown-unknown-eabi"
> -
> -define i64 @test_tstart() #0 {
> - %r = tail call i64 @llvm.aarch64.tstart()
> - ret i64 %r
> -}
> -
> -declare i64 @llvm.aarch64.tstart() #1
> -
> -attributes #0 = { "target-features"="+tme" }
> -attributes #1 = { nounwind }
> -
> -; CHECK-LABEL: test_tstart
> -; CHECK: tstart x
>
> Removed: llvm/trunk/test/CodeGen/AArch64/tme-ttest.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/tme-ttest.ll?rev=366354&view=auto
> ==============================================================================
> --- llvm/trunk/test/CodeGen/AArch64/tme-ttest.ll (original)
> +++ llvm/trunk/test/CodeGen/AArch64/tme-ttest.ll (removed)
> @@ -1,16 +0,0 @@
> -; RUN: llc %s -o - | FileCheck %s
> -
> -target triple = "aarch64-unknown-unknown-eabi"
> -
> -define i64 @test_ttest() #0 {
> - %r = tail call i64 @llvm.aarch64.ttest()
> - ret i64 %r
> -}
> -
> -declare i64 @llvm.aarch64.ttest() #1
> -
> -attributes #0 = { "target-features"="+tme" }
> -attributes #1 = { nounwind }
> -
> -; CHECK-LABEL: test_ttest
> -; CHECK: ttest x
>
> Removed: llvm/trunk/test/MC/AArch64/tme-error.s
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/tme-error.s?rev=366354&view=auto
> ==============================================================================
> --- llvm/trunk/test/MC/AArch64/tme-error.s (original)
> +++ llvm/trunk/test/MC/AArch64/tme-error.s (removed)
> @@ -1,47 +0,0 @@
> -// Tests for transactional memory extension instructions
> -// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=+tme < %s 2>&1 | FileCheck %s
> -
> -tstart
> -// CHECK: error: too few operands for instruction
> -// CHECK-NEXT: tstart
> -tstart x4, x5
> -// CHECK: error: invalid operand for instruction
> -// CHECK-NEXT: tstart x4, x5
> -tstart x4, #1
> -// CHECK: error: invalid operand for instruction
> -// CHECK-NEXT: tstart x4, #1
> -tstart sp
> -// CHECK: error: invalid operand for instruction
> -// CHECK-NEXT: tstart sp
> -
> -ttest
> -// CHECK: error: too few operands for instruction
> -// CHECK-NEXT: ttest
> -ttest x4, x5
> -// CHECK: error: invalid operand for instruction
> -// CHECK-NEXT: ttest x4, x5
> -ttest x4, #1
> -// CHECK: error: invalid operand for instruction
> -// CHECK-NEXT: ttest x4, #1
> -ttest sp
> -// CHECK: error: invalid operand for instruction
> -// CHECK-NEXT: ttest sp
> -
> -tcommit x4
> -// CHECK: error: invalid operand for instruction
> -// CHECK-NEXT: tcommit x4
> -tcommit sp
> -// CHECK: error: invalid operand for instruction
> -// CHECK-NEXT: tcommit sp
> -
> -
> -tcancel
> -// CHECK: error: too few operands for instruction
> -// CHECK-NEXT tcancel
> -tcancel x0
> -// CHECK: error: immediate must be an integer in range [0, 65535]
> -// CHECK-NEXT tcancel
> -tcancel #65536
> -// CHECK: error: immediate must be an integer in range [0, 65535]
> -// CHECK-NEXT: tcancel #65536
> -
>
> Removed: llvm/trunk/test/MC/AArch64/tme.s
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/tme.s?rev=366354&view=auto
> ==============================================================================
> --- llvm/trunk/test/MC/AArch64/tme.s (original)
> +++ llvm/trunk/test/MC/AArch64/tme.s (removed)
> @@ -1,24 +0,0 @@
> -// Tests for transaction memory extension instructions
> -//
> -// RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+tme < %s | FileCheck %s
> -// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=-tme < %s 2>&1 | FileCheck %s --check-prefix=NOTME
> -
> -tstart x3
> -ttest x4
> -tcommit
> -tcancel #0x1234
> -
> -// CHECK: tstart x3 // encoding: [0x63,0x30,0x23,0xd5]
> -// CHECK: ttest x4 // encoding: [0x64,0x31,0x23,0xd5]
> -// CHECK: tcommit // encoding: [0x7f,0x30,0x03,0xd5]
> -// CHECK: tcancel #0x1234 // encoding: [0x80,0x46,0x62,0xd4]
> -
> -
> -// NOTME: instruction requires: tme
> -// NOTME-NEXT: tstart x3
> -// NOTME: instruction requires: tme
> -// NOTME-NEXT: ttest x4
> -// NOTME: instruction requires: tme
> -// NOTME-NEXT: tcommit
> -// NOTME: instruction requires: tme
> -// NOTME-NEXT: tcancel #0x1234
>
> Removed: llvm/trunk/test/MC/Disassembler/AArch64/tme.txt
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AArch64/tme.txt?rev=366354&view=auto
> ==============================================================================
> --- llvm/trunk/test/MC/Disassembler/AArch64/tme.txt (original)
> +++ llvm/trunk/test/MC/Disassembler/AArch64/tme.txt (removed)
> @@ -1,19 +0,0 @@
> -# Tests for transaction memory extension instructions
> -# RUN: llvm-mc -triple=aarch64 -mattr=+tme -disassemble < %s | FileCheck %s
> -# RUN: not llvm-mc -triple=aarch64 -mattr=-tme -disassemble < %s 2>&1 | FileCheck %s --check-prefix=NOTME
> -
> -[0x63,0x30,0x23,0xd5]
> -[0x64,0x31,0x23,0xd5]
> -[0x7f,0x30,0x03,0xd5]
> -[0x80,0x46,0x62,0xd4]
> -
> -# CHECK: tstart x3
> -# CHECK: ttest x4
> -# CHECK: tcommit
> -# CHECK: tcancel #0x1234
> -
> -# NOTEME: mrs
> -# NOTEME-NEXT: mrs
> -# NOTEME-NEXT: msr
> -# NOTME: warning: invalid instruction encoding
> -# NOTME-NEXT: [0x80,0x46,0x62,0xd4]
>
> Modified: llvm/trunk/unittests/Support/TargetParserTest.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/Support/TargetParserTest.cpp?rev=366355&r1=366354&r2=366355&view=diff
> ==============================================================================
> --- llvm/trunk/unittests/Support/TargetParserTest.cpp (original)
> +++ llvm/trunk/unittests/Support/TargetParserTest.cpp Wed Jul 17 10:43:32 2019
> @@ -1119,7 +1119,6 @@ TEST(TargetParserTest, AArch64ArchExtFea
> {"rcpc", "norcpc", "+rcpc", "-rcpc" },
> {"rng", "norng", "+rand", "-rand"},
> {"memtag", "nomemtag", "+mte", "-mte"},
> - {"tme", "notme", "+tme", "-tme"},
> {"ssbs", "nossbs", "+ssbs", "-ssbs"},
> {"sb", "nosb", "+sb", "-sb"},
> {"predres", "nopredres", "+predres", "-predres"}
>
>
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