[PATCH] D64839: [AMDGPU] Autogenerate register asm names

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec marked 2 inline comments as done.
rampitec added inline comments.


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Comment at: lib/Target/AMDGPU/SIRegisterInfo.td:61
+                [ prefix # regNo,
+                  prefix # "[" # regNo # ":" # !and(!add(regNo, 1), 255) # "]",
+                  prefix # "[" # regNo # ":" # !and(!add(regNo, 2), 255) # "]",
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arsenm wrote:
> So this generates too many names, and then the extra SGPR ones just don't work?
It generates a practical minimum of used names with exception of:
1. It generates overflow names, like v[255:0]. We do not use overflow regs, but in fact we could.
2. It generates dups for special registers, but there are not too much of them.

Generic names can be dropped in a separate patch in favor of Reg32, but that will be a separate huge tests update. I thought of that but do not want to mix everything into a single change. I am also not sure how mir will live with square brackets and colons.


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Comment at: lib/Target/AMDGPU/SIRegisterInfo.td:634
 def Pseudo_SReg_128 : RegisterClass<"AMDGPU", [v4i32, v2i64, v2f64], 32,
-  (add PRIVATE_RSRC_REG)> {
+  (add PRIVATE_RSRC_REG), Reg32> {
   let isAllocatable = 0;
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arsenm wrote:
> This probably shouldn't have a set name, but should be Reg128
Thanks, Reg128 indeed.


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  https://reviews.llvm.org/D64839/new/

https://reviews.llvm.org/D64839