[PATCH] D64830: [Xtensa 4/10] Add basic *td files with Xtensa architecture description.

[Andrei Safronov via Phabricator via llvm-commits]

andreisfr created this revision.
andreisfr added reviewers: jyknight, ivanbaev.
Herald added subscribers: llvm-commits, hiraditya, mgorny.
Herald added a project: LLVM.

Add initial Xtensa.td file with target machine description. Add XtensaInstrInfo.td,
currently describe just susbet of Core Instructions like ALU, Processor control,
memory barrier and some move instructions. Add descriptions of the instructions
formats(XtensaInstrInfo.td) and some immediate instruction operands(XtensaOperands.td).
Add General Registers and Special Registers classes.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D64830

Files:
  llvm/lib/Target/Xtensa/CMakeLists.txt
  llvm/lib/Target/Xtensa/Xtensa.td
  llvm/lib/Target/Xtensa/XtensaInstrFormats.td
  llvm/lib/Target/Xtensa/XtensaInstrInfo.td
  llvm/lib/Target/Xtensa/XtensaOperands.td
  llvm/lib/Target/Xtensa/XtensaRegisterInfo.td

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D64830.210197.patch
Type: text/x-patch
Size: 19044 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20190716/e6d45cf7/attachment.bin>