[llvm] r366257 - AMDGPU/GlobalISel: Select G_ASHR
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 16 13:31:25 PDT 2019
Author: arsenm
Date: Tue Jul 16 13:31:25 2019
New Revision: 366257
URL: http://llvm.org/viewvc/llvm-project?rev=366257&view=rev
Log:
AMDGPU/GlobalISel: Select G_ASHR
Added:
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.s16.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.v2s16.mir
Modified:
llvm/trunk/lib/Target/AMDGPU/AMDGPUGISel.td
llvm/trunk/lib/Target/AMDGPU/SOPInstructions.td
llvm/trunk/lib/Target/AMDGPU/VOP2Instructions.td
llvm/trunk/lib/Target/AMDGPU/VOP3Instructions.td
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.mir
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUGISel.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUGISel.td?rev=366257&r1=366256&r2=366257&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUGISel.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUGISel.td Tue Jul 16 13:31:25 2019
@@ -143,15 +143,6 @@ multiclass GISelVop2IntrPat <
def : GISelSop2Pat <or, S_OR_B32, i32>;
def : GISelVop2Pat <or, V_OR_B32_e32, i32>;
-def : GISelSop2Pat <sra, S_ASHR_I32, i32>;
-let AddedComplexity = 100 in {
-let SubtargetPredicate = isGFX6GFX7 in {
-def : GISelVop2Pat <sra, V_ASHR_I32_e32, i32>;
-}
-def : GISelVop2CommutePat <sra, V_ASHRREV_I32_e32, i32>;
-}
-def : GISelVop3Pat2CommutePat <sra, V_ASHRREV_I32_e64, i32>;
-
// FIXME: We can't re-use SelectionDAG patterns here because they match
// against a custom SDNode and we would need to create a generic machine
// instruction that is equivalent to the custom SDNode. This would also require
Modified: llvm/trunk/lib/Target/AMDGPU/SOPInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SOPInstructions.td?rev=366257&r1=366256&r2=366257&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SOPInstructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/SOPInstructions.td Tue Jul 16 13:31:25 2019
@@ -523,10 +523,10 @@ def S_LSHR_B64 : SOP2_64_32 <"s_lshr_b64
[(set SReg_64:$sdst, (srl (i64 SSrc_b64:$src0), (i32 SSrc_b32:$src1)))]
>;
def S_ASHR_I32 : SOP2_32 <"s_ashr_i32",
- [(set i32:$sdst, (UniformBinFrag<sra> i32:$src0, i32:$src1))]
+ [(set SReg_32:$sdst, (sra (i32 SSrc_b32:$src0), (i32 SSrc_b32:$src1)))]
>;
def S_ASHR_I64 : SOP2_64_32 <"s_ashr_i64",
- [(set i64:$sdst, (UniformBinFrag<sra> i64:$src0, i32:$src1))]
+ [(set SReg_64:$sdst, (sra (i64 SSrc_b64:$src0), (i32 SSrc_b32:$src1)))]
>;
} // End Defs = [SCC]
Modified: llvm/trunk/lib/Target/AMDGPU/VOP2Instructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/VOP2Instructions.td?rev=366257&r1=366256&r2=366257&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/VOP2Instructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/VOP2Instructions.td Tue Jul 16 13:31:25 2019
@@ -473,7 +473,7 @@ defm V_MAX_I32 : VOP2Inst <"v_max_i32",
defm V_MIN_U32 : VOP2Inst <"v_min_u32", VOP_PAT_GEN<VOP_I32_I32_I32>, umin>;
defm V_MAX_U32 : VOP2Inst <"v_max_u32", VOP_PAT_GEN<VOP_I32_I32_I32>, umax>;
defm V_LSHRREV_B32 : VOP2Inst <"v_lshrrev_b32", VOP_I32_I32_I32, lshr_rev, "v_lshr_b32">;
-defm V_ASHRREV_I32 : VOP2Inst <"v_ashrrev_i32", VOP_I32_I32_I32, null_frag, "v_ashr_i32">;
+defm V_ASHRREV_I32 : VOP2Inst <"v_ashrrev_i32", VOP_I32_I32_I32, ashr_rev, "v_ashr_i32">;
defm V_LSHLREV_B32 : VOP2Inst <"v_lshlrev_b32", VOP_I32_I32_I32, lshl_rev, "v_lshl_b32">;
defm V_AND_B32 : VOP2Inst <"v_and_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, and>;
defm V_OR_B32 : VOP2Inst <"v_or_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, or>;
Modified: llvm/trunk/lib/Target/AMDGPU/VOP3Instructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/VOP3Instructions.td?rev=366257&r1=366256&r2=366257&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/VOP3Instructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/VOP3Instructions.td Tue Jul 16 13:31:25 2019
@@ -395,7 +395,7 @@ def V_MULLIT_F32 : VOP3Inst <"v_mullit_f
let SubtargetPredicate = isGFX8Plus in {
def V_LSHLREV_B64 : VOP3Inst <"v_lshlrev_b64", VOP3_Profile<VOP_I64_I32_I64>, lshl_rev>;
def V_LSHRREV_B64 : VOP3Inst <"v_lshrrev_b64", VOP3_Profile<VOP_I64_I32_I64>, lshr_rev>;
-def V_ASHRREV_I64 : VOP3Inst <"v_ashrrev_i64", VOP3_Profile<VOP_I64_I32_I64>>;
+def V_ASHRREV_I64 : VOP3Inst <"v_ashrrev_i64", VOP3_Profile<VOP_I64_I32_I64>, ashr_rev>;
} // End SubtargetPredicate = isGFX8Plus
} // End SchedRW = [Write64Bit]
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.mir?rev=366257&r1=366256&r2=366257&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.mir Tue Jul 16 13:31:25 2019
@@ -1,82 +1,327 @@
-# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN,SI
-# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN,VI
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX6 %s
+# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX7 %s
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX8 %s
+# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX9 %s
+# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX10 %s
---
-
-name: ashr
-legalized: true
+name: ashr_s32_ss
+legalized: true
regBankSelected: true
-# GCN-LABEL: name: ashr
body: |
bb.0:
- liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr3_vgpr4
- ; GCN: [[SGPR0:%[0-9]+]]:sreg_32 = COPY $sgpr0
- ; GCN: [[SGPR1:%[0-9]+]]:sreg_32 = COPY $sgpr1
- ; GCN: [[VGPR0:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ liveins: $sgpr0, $sgpr1
+ ; GFX6-LABEL: name: ashr_s32_ss
+ ; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+ ; GFX6: [[S_ASHR_I32_:%[0-9]+]]:sreg_32 = S_ASHR_I32 [[COPY]], [[COPY1]], implicit-def $scc
+ ; GFX6: S_ENDPGM 0, implicit [[S_ASHR_I32_]]
+ ; GFX7-LABEL: name: ashr_s32_ss
+ ; GFX7: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX7: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+ ; GFX7: [[S_ASHR_I32_:%[0-9]+]]:sreg_32 = S_ASHR_I32 [[COPY]], [[COPY1]], implicit-def $scc
+ ; GFX7: S_ENDPGM 0, implicit [[S_ASHR_I32_]]
+ ; GFX8-LABEL: name: ashr_s32_ss
+ ; GFX8: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+ ; GFX8: [[S_ASHR_I32_:%[0-9]+]]:sreg_32 = S_ASHR_I32 [[COPY]], [[COPY1]], implicit-def $scc
+ ; GFX8: S_ENDPGM 0, implicit [[S_ASHR_I32_]]
+ ; GFX9-LABEL: name: ashr_s32_ss
+ ; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+ ; GFX9: [[S_ASHR_I32_:%[0-9]+]]:sreg_32 = S_ASHR_I32 [[COPY]], [[COPY1]], implicit-def $scc
+ ; GFX9: S_ENDPGM 0, implicit [[S_ASHR_I32_]]
+ ; GFX10-LABEL: name: ashr_s32_ss
+ ; GFX10: $vcc_hi = IMPLICIT_DEF
+ ; GFX10: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+ ; GFX10: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
+ ; GFX10: [[S_ASHR_I32_:%[0-9]+]]:sreg_32 = S_ASHR_I32 [[COPY]], [[COPY1]], implicit-def $scc
+ ; GFX10: S_ENDPGM 0, implicit [[S_ASHR_I32_]]
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = COPY $sgpr1
- %2:vgpr(s32) = COPY $vgpr0
- %3:vgpr(p1) = COPY $vgpr3_vgpr4
+ %2:sgpr(s32) = G_ASHR %0, %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: ashr_s32_sv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $vgpr0
+ ; GFX6-LABEL: name: ashr_s32_sv
+ ; GFX6: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX6: [[V_ASHRREV_I32_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[COPY1]], [[COPY]], implicit $exec
+ ; GFX6: S_ENDPGM 0, implicit [[V_ASHRREV_I32_e64_]]
+ ; GFX7-LABEL: name: ashr_s32_sv
+ ; GFX7: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX7: [[V_ASHRREV_I32_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[COPY1]], [[COPY]], implicit $exec
+ ; GFX7: S_ENDPGM 0, implicit [[V_ASHRREV_I32_e64_]]
+ ; GFX8-LABEL: name: ashr_s32_sv
+ ; GFX8: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX8: [[V_ASHRREV_I32_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[COPY1]], [[COPY]], implicit $exec
+ ; GFX8: S_ENDPGM 0, implicit [[V_ASHRREV_I32_e64_]]
+ ; GFX9-LABEL: name: ashr_s32_sv
+ ; GFX9: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX9: [[V_ASHRREV_I32_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[COPY1]], [[COPY]], implicit $exec
+ ; GFX9: S_ENDPGM 0, implicit [[V_ASHRREV_I32_e64_]]
+ ; GFX10-LABEL: name: ashr_s32_sv
+ ; GFX10: $vcc_hi = IMPLICIT_DEF
+ ; GFX10: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX10: [[V_ASHRREV_I32_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[COPY1]], [[COPY]], implicit $exec
+ ; GFX10: S_ENDPGM 0, implicit [[V_ASHRREV_I32_e64_]]
+ %0:sgpr(s32) = COPY $sgpr0
+ %1:vgpr(s32) = COPY $vgpr0
+ %2:vgpr(s32) = G_ASHR %0, %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: ashr_s32_vs
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $vgpr0
+ ; GFX6-LABEL: name: ashr_s32_vs
+ ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX6: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; GFX6: [[V_ASHRREV_I32_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[COPY1]], [[COPY]], implicit $exec
+ ; GFX6: S_ENDPGM 0, implicit [[V_ASHRREV_I32_e64_]]
+ ; GFX7-LABEL: name: ashr_s32_vs
+ ; GFX7: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX7: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; GFX7: [[V_ASHRREV_I32_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[COPY1]], [[COPY]], implicit $exec
+ ; GFX7: S_ENDPGM 0, implicit [[V_ASHRREV_I32_e64_]]
+ ; GFX8-LABEL: name: ashr_s32_vs
+ ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX8: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; GFX8: [[V_ASHRREV_I32_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[COPY1]], [[COPY]], implicit $exec
+ ; GFX8: S_ENDPGM 0, implicit [[V_ASHRREV_I32_e64_]]
+ ; GFX9-LABEL: name: ashr_s32_vs
+ ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX9: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; GFX9: [[V_ASHRREV_I32_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[COPY1]], [[COPY]], implicit $exec
+ ; GFX9: S_ENDPGM 0, implicit [[V_ASHRREV_I32_e64_]]
+ ; GFX10-LABEL: name: ashr_s32_vs
+ ; GFX10: $vcc_hi = IMPLICIT_DEF
+ ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX10: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; GFX10: [[V_ASHRREV_I32_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[COPY1]], [[COPY]], implicit $exec
+ ; GFX10: S_ENDPGM 0, implicit [[V_ASHRREV_I32_e64_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:sgpr(s32) = COPY $sgpr0
+ %2:vgpr(s32) = G_ASHR %0, %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: ashr_s32_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; GFX6-LABEL: name: ashr_s32_vv
+ ; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX6: [[V_ASHRREV_I32_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[COPY1]], [[COPY]], implicit $exec
+ ; GFX6: S_ENDPGM 0, implicit [[V_ASHRREV_I32_e64_]]
+ ; GFX7-LABEL: name: ashr_s32_vv
+ ; GFX7: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX7: [[V_ASHRREV_I32_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[COPY1]], [[COPY]], implicit $exec
+ ; GFX7: S_ENDPGM 0, implicit [[V_ASHRREV_I32_e64_]]
+ ; GFX8-LABEL: name: ashr_s32_vv
+ ; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX8: [[V_ASHRREV_I32_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[COPY1]], [[COPY]], implicit $exec
+ ; GFX8: S_ENDPGM 0, implicit [[V_ASHRREV_I32_e64_]]
+ ; GFX9-LABEL: name: ashr_s32_vv
+ ; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX9: [[V_ASHRREV_I32_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[COPY1]], [[COPY]], implicit $exec
+ ; GFX9: S_ENDPGM 0, implicit [[V_ASHRREV_I32_e64_]]
+ ; GFX10-LABEL: name: ashr_s32_vv
+ ; GFX10: $vcc_hi = IMPLICIT_DEF
+ ; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+ ; GFX10: [[V_ASHRREV_I32_e64_:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[COPY1]], [[COPY]], implicit $exec
+ ; GFX10: S_ENDPGM 0, implicit [[V_ASHRREV_I32_e64_]]
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr1
+ %2:vgpr(s32) = G_ASHR %0, %1
+ S_ENDPGM 0, implicit %2
+...
- ; GCN: [[C1:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 1
- ; GCN: [[C4096:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 4096
- %4:sgpr(s32) = G_CONSTANT i32 1
- %5:sgpr(s32) = G_CONSTANT i32 4096
-
- ; ashr ss
- ; GCN: [[SS:%[0-9]+]]:sreg_32 = S_ASHR_I32 [[SGPR0]], [[SGPR1]]
- %6:sgpr(s32) = G_ASHR %0, %1
-
- ; ashr si
- ; GCN: [[SI:%[0-9]+]]:sreg_32 = S_ASHR_I32 [[SS]], [[C1]]
- %7:sgpr(s32) = G_ASHR %6, %4
-
- ; ashr is
- ; GCN: [[IS:%[0-9]+]]:sreg_32 = S_ASHR_I32 [[C1]], [[SI]]
- %8:sgpr(s32) = G_ASHR %4, %7
-
- ; ashr sc
- ; GCN: [[SC:%[0-9]+]]:sreg_32 = S_ASHR_I32 [[IS]], [[C4096]]
- %9:sgpr(s32) = G_ASHR %8, %5
-
- ; ashr cs
- ; GCN: [[CS:%[0-9]+]]:sreg_32_xm0 = S_ASHR_I32 [[C4096]], [[SC]]
- %10:sgpr(s32) = G_ASHR %5, %9
-
- ; ashr vs
- ; GCN: [[VS:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e32 [[CS]], [[VGPR0]]
- %11:vgpr(s32) = G_ASHR %2, %10
-
- ; ashr sv
- ; SI: [[SV:%[0-9]+]]:vgpr_32 = V_ASHR_I32_e32 [[CS]], [[VS]]
- ; VI: [[SV:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[VS]], [[CS]]
- %12:vgpr(s32) = G_ASHR %10, %11
-
- ; ashr vv
- ; SI: [[VV:%[0-9]+]]:vgpr_32 = V_ASHR_I32_e32 [[SV]], [[VGPR0]]
- ; VI: [[VV:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e32 [[VGPR0]], [[SV]]
- %13:vgpr(s32) = G_ASHR %12, %2
-
- ; ashr iv
- ; SI: [[IV:%[0-9]+]]:vgpr_32 = V_ASHR_I32_e32 [[C1]], [[VV]]
- ; VI: [[IV:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[VV]], [[C1]]
- %14:vgpr(s32) = G_ASHR %4, %13
-
- ; ashr vi
- ; GCN: [[VI:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e32 [[C1]], [[IV]]
- %15:vgpr(s32) = G_ASHR %14, %4
-
- ; ashr cv
- ; SI: [[CV:%[0-9]+]]:vgpr_32 = V_ASHR_I32_e32 [[C4096]], [[VI]]
- ; VI: [[CV:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e64 [[VI]], [[C4096]]
- %16:vgpr(s32) = G_ASHR %5, %15
-
- ; ashr vc
- ; GCN: [[VC:%[-1-9]+]]:vgpr_32 = V_ASHRREV_I32_e32 [[C4096]], [[CV]]
- %17:vgpr(s32) = G_ASHR %16, %5
+---
+name: ashr_s64_ss
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1, $sgpr2
+ ; GFX6-LABEL: name: ashr_s64_ss
+ ; GFX6: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
+ ; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
+ ; GFX6: [[S_ASHR_I64_:%[0-9]+]]:sreg_64 = S_ASHR_I64 [[COPY]], [[COPY1]], implicit-def $scc
+ ; GFX6: S_ENDPGM 0, implicit [[S_ASHR_I64_]]
+ ; GFX7-LABEL: name: ashr_s64_ss
+ ; GFX7: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
+ ; GFX7: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
+ ; GFX7: [[S_ASHR_I64_:%[0-9]+]]:sreg_64 = S_ASHR_I64 [[COPY]], [[COPY1]], implicit-def $scc
+ ; GFX7: S_ENDPGM 0, implicit [[S_ASHR_I64_]]
+ ; GFX8-LABEL: name: ashr_s64_ss
+ ; GFX8: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
+ ; GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
+ ; GFX8: [[S_ASHR_I64_:%[0-9]+]]:sreg_64 = S_ASHR_I64 [[COPY]], [[COPY1]], implicit-def $scc
+ ; GFX8: S_ENDPGM 0, implicit [[S_ASHR_I64_]]
+ ; GFX9-LABEL: name: ashr_s64_ss
+ ; GFX9: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
+ ; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
+ ; GFX9: [[S_ASHR_I64_:%[0-9]+]]:sreg_64 = S_ASHR_I64 [[COPY]], [[COPY1]], implicit-def $scc
+ ; GFX9: S_ENDPGM 0, implicit [[S_ASHR_I64_]]
+ ; GFX10-LABEL: name: ashr_s64_ss
+ ; GFX10: $vcc_hi = IMPLICIT_DEF
+ ; GFX10: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
+ ; GFX10: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
+ ; GFX10: [[S_ASHR_I64_:%[0-9]+]]:sreg_64 = S_ASHR_I64 [[COPY]], [[COPY1]], implicit-def $scc
+ ; GFX10: S_ENDPGM 0, implicit [[S_ASHR_I64_]]
+ %0:sgpr(s64) = COPY $sgpr0_sgpr1
+ %1:sgpr(s32) = COPY $sgpr2
+ %2:sgpr(s64) = G_ASHR %0, %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: ashr_s64_sv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1, $vgpr0
+ ; GFX6-LABEL: name: ashr_s64_sv
+ ; GFX6: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
+ ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX6: [[V_ASHRREV_I64_:%[0-9]+]]:vreg_64 = V_ASHRREV_I64 [[COPY1]], [[COPY]], implicit $exec
+ ; GFX6: S_ENDPGM 0, implicit [[V_ASHRREV_I64_]]
+ ; GFX7-LABEL: name: ashr_s64_sv
+ ; GFX7: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
+ ; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX7: [[V_ASHRREV_I64_:%[0-9]+]]:vreg_64 = V_ASHRREV_I64 [[COPY1]], [[COPY]], implicit $exec
+ ; GFX7: S_ENDPGM 0, implicit [[V_ASHRREV_I64_]]
+ ; GFX8-LABEL: name: ashr_s64_sv
+ ; GFX8: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
+ ; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX8: [[V_ASHRREV_I64_:%[0-9]+]]:vreg_64 = V_ASHRREV_I64 [[COPY1]], [[COPY]], implicit $exec
+ ; GFX8: S_ENDPGM 0, implicit [[V_ASHRREV_I64_]]
+ ; GFX9-LABEL: name: ashr_s64_sv
+ ; GFX9: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
+ ; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX9: [[V_ASHRREV_I64_:%[0-9]+]]:vreg_64 = V_ASHRREV_I64 [[COPY1]], [[COPY]], implicit $exec
+ ; GFX9: S_ENDPGM 0, implicit [[V_ASHRREV_I64_]]
+ ; GFX10-LABEL: name: ashr_s64_sv
+ ; GFX10: $vcc_hi = IMPLICIT_DEF
+ ; GFX10: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
+ ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX10: [[V_ASHRREV_I64_:%[0-9]+]]:vreg_64 = V_ASHRREV_I64 [[COPY1]], [[COPY]], implicit $exec
+ ; GFX10: S_ENDPGM 0, implicit [[V_ASHRREV_I64_]]
+ %0:sgpr(s64) = COPY $sgpr0_sgpr1
+ %1:vgpr(s32) = COPY $vgpr0
+ %2:vgpr(s64) = G_ASHR %0, %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: ashr_s64_vs
+legalized: true
+regBankSelected: true
+body: |
+ bb.0:
+ liveins: $sgpr0, $vgpr0_vgpr1
+ ; GFX6-LABEL: name: ashr_s64_vs
+ ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; GFX6: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; GFX6: [[V_ASHRREV_I64_:%[0-9]+]]:vreg_64 = V_ASHRREV_I64 [[COPY1]], [[COPY]], implicit $exec
+ ; GFX6: S_ENDPGM 0, implicit [[V_ASHRREV_I64_]]
+ ; GFX7-LABEL: name: ashr_s64_vs
+ ; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; GFX7: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; GFX7: [[V_ASHRREV_I64_:%[0-9]+]]:vreg_64 = V_ASHRREV_I64 [[COPY1]], [[COPY]], implicit $exec
+ ; GFX7: S_ENDPGM 0, implicit [[V_ASHRREV_I64_]]
+ ; GFX8-LABEL: name: ashr_s64_vs
+ ; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; GFX8: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; GFX8: [[V_ASHRREV_I64_:%[0-9]+]]:vreg_64 = V_ASHRREV_I64 [[COPY1]], [[COPY]], implicit $exec
+ ; GFX8: S_ENDPGM 0, implicit [[V_ASHRREV_I64_]]
+ ; GFX9-LABEL: name: ashr_s64_vs
+ ; GFX9: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; GFX9: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; GFX9: [[V_ASHRREV_I64_:%[0-9]+]]:vreg_64 = V_ASHRREV_I64 [[COPY1]], [[COPY]], implicit $exec
+ ; GFX9: S_ENDPGM 0, implicit [[V_ASHRREV_I64_]]
+ ; GFX10-LABEL: name: ashr_s64_vs
+ ; GFX10: $vcc_hi = IMPLICIT_DEF
+ ; GFX10: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; GFX10: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; GFX10: [[V_ASHRREV_I64_:%[0-9]+]]:vreg_64 = V_ASHRREV_I64 [[COPY1]], [[COPY]], implicit $exec
+ ; GFX10: S_ENDPGM 0, implicit [[V_ASHRREV_I64_]]
+ %0:vgpr(s64) = COPY $vgpr0_vgpr1
+ %1:sgpr(s32) = COPY $sgpr0
+ %2:vgpr(s64) = G_ASHR %0, %1
+ S_ENDPGM 0, implicit %2
+...
- S_ENDPGM 0, implicit %17
+---
+name: ashr_s64_vv
+legalized: true
+regBankSelected: true
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1, $vgpr2
+ ; GFX6-LABEL: name: ashr_s64_vv
+ ; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; GFX6: [[V_ASHRREV_I64_:%[0-9]+]]:vreg_64 = V_ASHRREV_I64 [[COPY1]], [[COPY]], implicit $exec
+ ; GFX6: S_ENDPGM 0, implicit [[V_ASHRREV_I64_]]
+ ; GFX7-LABEL: name: ashr_s64_vv
+ ; GFX7: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; GFX7: [[V_ASHRREV_I64_:%[0-9]+]]:vreg_64 = V_ASHRREV_I64 [[COPY1]], [[COPY]], implicit $exec
+ ; GFX7: S_ENDPGM 0, implicit [[V_ASHRREV_I64_]]
+ ; GFX8-LABEL: name: ashr_s64_vv
+ ; GFX8: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; GFX8: [[V_ASHRREV_I64_:%[0-9]+]]:vreg_64 = V_ASHRREV_I64 [[COPY1]], [[COPY]], implicit $exec
+ ; GFX8: S_ENDPGM 0, implicit [[V_ASHRREV_I64_]]
+ ; GFX9-LABEL: name: ashr_s64_vv
+ ; GFX9: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; GFX9: [[V_ASHRREV_I64_:%[0-9]+]]:vreg_64 = V_ASHRREV_I64 [[COPY1]], [[COPY]], implicit $exec
+ ; GFX9: S_ENDPGM 0, implicit [[V_ASHRREV_I64_]]
+ ; GFX10-LABEL: name: ashr_s64_vv
+ ; GFX10: $vcc_hi = IMPLICIT_DEF
+ ; GFX10: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
+ ; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+ ; GFX10: [[V_ASHRREV_I64_:%[0-9]+]]:vreg_64 = V_ASHRREV_I64 [[COPY1]], [[COPY]], implicit $exec
+ ; GFX10: S_ENDPGM 0, implicit [[V_ASHRREV_I64_]]
+ %0:vgpr(s64) = COPY $vgpr0_vgpr1
+ %1:vgpr(s32) = COPY $vgpr2
+ %2:vgpr(s64) = G_ASHR %0, %1
+ S_ENDPGM 0, implicit %2
...
+
Added: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.s16.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.s16.mir?rev=366257&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.s16.mir (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.s16.mir Tue Jul 16 13:31:25 2019
@@ -0,0 +1,203 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+
+# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -global-isel-abort=2 -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o - 2>%t | FileCheck -check-prefix=GFX8 %s
+# RUN: FileCheck -check-prefixes=ERR-GFX8,ERR %s < %t
+
+# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -global-isel-abort=2 -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o - 2>%t | FileCheck -check-prefix=GFX9 %s
+# RUN: FileCheck -check-prefixes=ERR-GFX910,ERR %s < %t
+
+# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -global-isel-abort=2 -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o - 2>%t | FileCheck -check-prefix=GFX10 %s
+# RUN: FileCheck -check-prefixes=ERR-GFX910,ERR %s < %t
+
+# ERR-NOT: remark
+# ERR-GFX8: remark: <unknown>:0:0: cannot select: %3:sgpr(s16) = G_ASHR %2:sgpr, %1:sgpr(s32) (in function: ashr_s16_ss)
+# ERR-GFX8-NEXT: remark: <unknown>:0:0: cannot select: %3:vgpr(s16) = G_ASHR %2:sgpr, %1:vgpr(s32) (in function: ashr_s16_sv)
+# ERR-GFX8-NEXT: remark: <unknown>:0:0: cannot select: %3:vgpr(s16) = G_ASHR %2:vgpr, %1:sgpr(s32) (in function: ashr_s16_vs)
+# ERR-GFX8-NEXT: remark: <unknown>:0:0: cannot select: %3:vgpr(s16) = G_ASHR %2:vgpr, %1:vgpr(s32) (in function: ashr_s16_vv)
+
+# ERR-GFX910: remark: <unknown>:0:0: cannot select: %3:sgpr(s16) = G_ASHR %2:sgpr, %1:sgpr(s32) (in function: ashr_s16_ss)
+# ERR-GFX910-NEXT: remark: <unknown>:0:0: cannot select: %3:vgpr(s16) = G_ASHR %2:sgpr, %1:vgpr(s32) (in function: ashr_s16_sv)
+# ERR-GFX910-NEXT: remark: <unknown>:0:0: cannot select: %3:vgpr(s16) = G_ASHR %2:vgpr, %1:sgpr(s32) (in function: ashr_s16_vs)
+# ERR-GFX910-NEXT: remark: <unknown>:0:0: cannot select: %3:vgpr(s16) = G_ASHR %2:vgpr, %1:vgpr(s32) (in function: ashr_s16_vv)
+
+# ERR-NOT: remark
+
+---
+name: ashr_s16_ss
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $sgpr1
+ ; GFX6-LABEL: name: ashr_s16_ss
+ ; GFX6: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GFX6: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; GFX6: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX6: [[ASHR:%[0-9]+]]:sgpr(s16) = G_ASHR [[TRUNC]], [[COPY1]](s32)
+ ; GFX6: S_ENDPGM 0, implicit [[ASHR]](s16)
+ ; GFX7-LABEL: name: ashr_s16_ss
+ ; GFX7: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GFX7: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; GFX7: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX7: [[ASHR:%[0-9]+]]:sgpr(s16) = G_ASHR [[TRUNC]], [[COPY1]](s32)
+ ; GFX7: S_ENDPGM 0, implicit [[ASHR]](s16)
+ ; GFX8-LABEL: name: ashr_s16_ss
+ ; GFX8: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GFX8: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; GFX8: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX8: [[ASHR:%[0-9]+]]:sgpr(s16) = G_ASHR [[TRUNC]], [[COPY1]](s32)
+ ; GFX8: S_ENDPGM 0, implicit [[ASHR]](s16)
+ ; GFX9-LABEL: name: ashr_s16_ss
+ ; GFX9: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GFX9: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; GFX9: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX9: [[ASHR:%[0-9]+]]:sgpr(s16) = G_ASHR [[TRUNC]], [[COPY1]](s32)
+ ; GFX9: S_ENDPGM 0, implicit [[ASHR]](s16)
+ ; GFX10-LABEL: name: ashr_s16_ss
+ ; GFX10: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GFX10: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
+ ; GFX10: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX10: [[ASHR:%[0-9]+]]:sgpr(s16) = G_ASHR [[TRUNC]], [[COPY1]](s32)
+ ; GFX10: S_ENDPGM 0, implicit [[ASHR]](s16)
+ %0:sgpr(s32) = COPY $sgpr0
+ %1:sgpr(s32) = COPY $sgpr1
+ %2:sgpr(s16) = G_TRUNC %0
+ %3:sgpr(s16) = G_ASHR %2, %1
+ S_ENDPGM 0, implicit %3
+...
+
+---
+name: ashr_s16_sv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $vgpr0
+ ; GFX6-LABEL: name: ashr_s16_sv
+ ; GFX6: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GFX6: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GFX6: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX6: [[ASHR:%[0-9]+]]:vgpr(s16) = G_ASHR [[TRUNC]], [[COPY1]](s32)
+ ; GFX6: S_ENDPGM 0, implicit [[ASHR]](s16)
+ ; GFX7-LABEL: name: ashr_s16_sv
+ ; GFX7: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GFX7: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GFX7: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX7: [[ASHR:%[0-9]+]]:vgpr(s16) = G_ASHR [[TRUNC]], [[COPY1]](s32)
+ ; GFX7: S_ENDPGM 0, implicit [[ASHR]](s16)
+ ; GFX8-LABEL: name: ashr_s16_sv
+ ; GFX8: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GFX8: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GFX8: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX8: [[ASHR:%[0-9]+]]:vgpr(s16) = G_ASHR [[TRUNC]], [[COPY1]](s32)
+ ; GFX8: S_ENDPGM 0, implicit [[ASHR]](s16)
+ ; GFX9-LABEL: name: ashr_s16_sv
+ ; GFX9: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GFX9: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GFX9: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX9: [[ASHR:%[0-9]+]]:vgpr(s16) = G_ASHR [[TRUNC]], [[COPY1]](s32)
+ ; GFX9: S_ENDPGM 0, implicit [[ASHR]](s16)
+ ; GFX10-LABEL: name: ashr_s16_sv
+ ; GFX10: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GFX10: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GFX10: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX10: [[ASHR:%[0-9]+]]:vgpr(s16) = G_ASHR [[TRUNC]], [[COPY1]](s32)
+ ; GFX10: S_ENDPGM 0, implicit [[ASHR]](s16)
+ %0:sgpr(s32) = COPY $sgpr0
+ %1:vgpr(s32) = COPY $vgpr0
+ %2:sgpr(s16) = G_TRUNC %0
+ %3:vgpr(s16) = G_ASHR %2, %1
+ S_ENDPGM 0, implicit %3
+...
+
+---
+name: ashr_s16_vs
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $vgpr0
+ ; GFX6-LABEL: name: ashr_s16_vs
+ ; GFX6: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GFX6: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GFX6: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX6: [[ASHR:%[0-9]+]]:vgpr(s16) = G_ASHR [[TRUNC]], [[COPY1]](s32)
+ ; GFX6: S_ENDPGM 0, implicit [[ASHR]](s16)
+ ; GFX7-LABEL: name: ashr_s16_vs
+ ; GFX7: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GFX7: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GFX7: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX7: [[ASHR:%[0-9]+]]:vgpr(s16) = G_ASHR [[TRUNC]], [[COPY1]](s32)
+ ; GFX7: S_ENDPGM 0, implicit [[ASHR]](s16)
+ ; GFX8-LABEL: name: ashr_s16_vs
+ ; GFX8: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GFX8: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GFX8: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX8: [[ASHR:%[0-9]+]]:vgpr(s16) = G_ASHR [[TRUNC]], [[COPY1]](s32)
+ ; GFX8: S_ENDPGM 0, implicit [[ASHR]](s16)
+ ; GFX9-LABEL: name: ashr_s16_vs
+ ; GFX9: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GFX9: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GFX9: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX9: [[ASHR:%[0-9]+]]:vgpr(s16) = G_ASHR [[TRUNC]], [[COPY1]](s32)
+ ; GFX9: S_ENDPGM 0, implicit [[ASHR]](s16)
+ ; GFX10-LABEL: name: ashr_s16_vs
+ ; GFX10: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GFX10: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GFX10: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX10: [[ASHR:%[0-9]+]]:vgpr(s16) = G_ASHR [[TRUNC]], [[COPY1]](s32)
+ ; GFX10: S_ENDPGM 0, implicit [[ASHR]](s16)
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:sgpr(s32) = COPY $sgpr0
+ %2:vgpr(s16) = G_TRUNC %0
+ %3:vgpr(s16) = G_ASHR %2, %1
+ S_ENDPGM 0, implicit %3
+...
+
+---
+name: ashr_s16_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; GFX6-LABEL: name: ashr_s16_vv
+ ; GFX6: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GFX6: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
+ ; GFX6: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX6: [[ASHR:%[0-9]+]]:vgpr(s16) = G_ASHR [[TRUNC]], [[COPY1]](s32)
+ ; GFX6: S_ENDPGM 0, implicit [[ASHR]](s16)
+ ; GFX7-LABEL: name: ashr_s16_vv
+ ; GFX7: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GFX7: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
+ ; GFX7: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX7: [[ASHR:%[0-9]+]]:vgpr(s16) = G_ASHR [[TRUNC]], [[COPY1]](s32)
+ ; GFX7: S_ENDPGM 0, implicit [[ASHR]](s16)
+ ; GFX8-LABEL: name: ashr_s16_vv
+ ; GFX8: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GFX8: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
+ ; GFX8: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX8: [[ASHR:%[0-9]+]]:vgpr(s16) = G_ASHR [[TRUNC]], [[COPY1]](s32)
+ ; GFX8: S_ENDPGM 0, implicit [[ASHR]](s16)
+ ; GFX9-LABEL: name: ashr_s16_vv
+ ; GFX9: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GFX9: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
+ ; GFX9: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX9: [[ASHR:%[0-9]+]]:vgpr(s16) = G_ASHR [[TRUNC]], [[COPY1]](s32)
+ ; GFX9: S_ENDPGM 0, implicit [[ASHR]](s16)
+ ; GFX10-LABEL: name: ashr_s16_vv
+ ; GFX10: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GFX10: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
+ ; GFX10: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX10: [[ASHR:%[0-9]+]]:vgpr(s16) = G_ASHR [[TRUNC]], [[COPY1]](s32)
+ ; GFX10: S_ENDPGM 0, implicit [[ASHR]](s16)
+ %0:vgpr(s32) = COPY $vgpr0
+ %1:vgpr(s32) = COPY $vgpr1
+ %2:vgpr(s16) = G_TRUNC %0
+ %3:vgpr(s16) = G_ASHR %2, %1
+ S_ENDPGM 0, implicit %3
+...
Added: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.v2s16.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.v2s16.mir?rev=366257&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.v2s16.mir (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.v2s16.mir Tue Jul 16 13:31:25 2019
@@ -0,0 +1,169 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -global-isel-abort=2 -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o - 2>%t | FileCheck -check-prefix=GFX9 %s
+# RUN: FileCheck -check-prefixes=ERR-GFX910,ERR %s < %t
+
+# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -global-isel-abort=2 -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o - 2>%t | FileCheck -check-prefix=GFX10 %s
+# RUN: FileCheck -check-prefixes=ERR-GFX910,ERR %s < %t
+
+# ERR-NOT: remark
+# ERR-GFX910: remark: <unknown>:0:0: cannot select: %2:sgpr(<2 x s16>) = G_ASHR %0:sgpr, %1:sgpr(<2 x s16>) (in function: ashr_v2s16_ss)
+# ERR-GFX910-NEXT: remark: <unknown>:0:0: cannot select: %2:vgpr(<2 x s16>) = G_ASHR %0:sgpr, %1:vgpr(<2 x s16>) (in function: ashr_v2s16_sv)
+# ERR-GFX910-NEXT: remark: <unknown>:0:0: cannot select: %2:vgpr(<2 x s16>) = G_ASHR %0:vgpr, %1:sgpr(<2 x s16>) (in function: ashr_v2s16_vs)
+# ERR-GFX910-NEXT: remark: <unknown>:0:0: cannot select: %2:vgpr(<2 x s16>) = G_ASHR %0:vgpr, %1:vgpr(<2 x s16>) (in function: ashr_v2s16_vv)
+# ERR-NOT: remark
+
+---
+name: ashr_v2s16_ss
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $sgpr1
+ ; GFX6-LABEL: name: ashr_v2s16_ss
+ ; GFX6: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
+ ; GFX6: [[COPY1:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr1
+ ; GFX6: [[ASHR:%[0-9]+]]:sgpr(<2 x s16>) = G_ASHR [[COPY]], [[COPY1]](<2 x s16>)
+ ; GFX6: S_ENDPGM 0, implicit [[ASHR]](<2 x s16>)
+ ; GFX7-LABEL: name: ashr_v2s16_ss
+ ; GFX7: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
+ ; GFX7: [[COPY1:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr1
+ ; GFX7: [[ASHR:%[0-9]+]]:sgpr(<2 x s16>) = G_ASHR [[COPY]], [[COPY1]](<2 x s16>)
+ ; GFX7: S_ENDPGM 0, implicit [[ASHR]](<2 x s16>)
+ ; GFX8-LABEL: name: ashr_v2s16_ss
+ ; GFX8: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
+ ; GFX8: [[COPY1:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr1
+ ; GFX8: [[ASHR:%[0-9]+]]:sgpr(<2 x s16>) = G_ASHR [[COPY]], [[COPY1]](<2 x s16>)
+ ; GFX8: S_ENDPGM 0, implicit [[ASHR]](<2 x s16>)
+ ; GFX9-LABEL: name: ashr_v2s16_ss
+ ; GFX9: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
+ ; GFX9: [[COPY1:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr1
+ ; GFX9: [[ASHR:%[0-9]+]]:sgpr(<2 x s16>) = G_ASHR [[COPY]], [[COPY1]](<2 x s16>)
+ ; GFX9: S_ENDPGM 0, implicit [[ASHR]](<2 x s16>)
+ ; GFX10-LABEL: name: ashr_v2s16_ss
+ ; GFX10: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
+ ; GFX10: [[COPY1:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr1
+ ; GFX10: [[ASHR:%[0-9]+]]:sgpr(<2 x s16>) = G_ASHR [[COPY]], [[COPY1]](<2 x s16>)
+ ; GFX10: S_ENDPGM 0, implicit [[ASHR]](<2 x s16>)
+ %0:sgpr(<2 x s16>) = COPY $sgpr0
+ %1:sgpr(<2 x s16>) = COPY $sgpr1
+ %2:sgpr(<2 x s16>) = G_ASHR %0, %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: ashr_v2s16_sv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $vgpr0
+ ; GFX6-LABEL: name: ashr_v2s16_sv
+ ; GFX6: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
+ ; GFX6: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
+ ; GFX6: [[ASHR:%[0-9]+]]:vgpr(<2 x s16>) = G_ASHR [[COPY]], [[COPY1]](<2 x s16>)
+ ; GFX6: S_ENDPGM 0, implicit [[ASHR]](<2 x s16>)
+ ; GFX7-LABEL: name: ashr_v2s16_sv
+ ; GFX7: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
+ ; GFX7: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
+ ; GFX7: [[ASHR:%[0-9]+]]:vgpr(<2 x s16>) = G_ASHR [[COPY]], [[COPY1]](<2 x s16>)
+ ; GFX7: S_ENDPGM 0, implicit [[ASHR]](<2 x s16>)
+ ; GFX8-LABEL: name: ashr_v2s16_sv
+ ; GFX8: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
+ ; GFX8: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
+ ; GFX8: [[ASHR:%[0-9]+]]:vgpr(<2 x s16>) = G_ASHR [[COPY]], [[COPY1]](<2 x s16>)
+ ; GFX8: S_ENDPGM 0, implicit [[ASHR]](<2 x s16>)
+ ; GFX9-LABEL: name: ashr_v2s16_sv
+ ; GFX9: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
+ ; GFX9: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
+ ; GFX9: [[ASHR:%[0-9]+]]:vgpr(<2 x s16>) = G_ASHR [[COPY]], [[COPY1]](<2 x s16>)
+ ; GFX9: S_ENDPGM 0, implicit [[ASHR]](<2 x s16>)
+ ; GFX10-LABEL: name: ashr_v2s16_sv
+ ; GFX10: [[COPY:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
+ ; GFX10: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
+ ; GFX10: [[ASHR:%[0-9]+]]:vgpr(<2 x s16>) = G_ASHR [[COPY]], [[COPY1]](<2 x s16>)
+ ; GFX10: S_ENDPGM 0, implicit [[ASHR]](<2 x s16>)
+ %0:sgpr(<2 x s16>) = COPY $sgpr0
+ %1:vgpr(<2 x s16>) = COPY $vgpr0
+ %2:vgpr(<2 x s16>) = G_ASHR %0, %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: ashr_v2s16_vs
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0, $vgpr0
+ ; GFX6-LABEL: name: ashr_v2s16_vs
+ ; GFX6: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
+ ; GFX6: [[COPY1:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
+ ; GFX6: [[ASHR:%[0-9]+]]:vgpr(<2 x s16>) = G_ASHR [[COPY]], [[COPY1]](<2 x s16>)
+ ; GFX6: S_ENDPGM 0, implicit [[ASHR]](<2 x s16>)
+ ; GFX7-LABEL: name: ashr_v2s16_vs
+ ; GFX7: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
+ ; GFX7: [[COPY1:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
+ ; GFX7: [[ASHR:%[0-9]+]]:vgpr(<2 x s16>) = G_ASHR [[COPY]], [[COPY1]](<2 x s16>)
+ ; GFX7: S_ENDPGM 0, implicit [[ASHR]](<2 x s16>)
+ ; GFX8-LABEL: name: ashr_v2s16_vs
+ ; GFX8: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
+ ; GFX8: [[COPY1:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
+ ; GFX8: [[ASHR:%[0-9]+]]:vgpr(<2 x s16>) = G_ASHR [[COPY]], [[COPY1]](<2 x s16>)
+ ; GFX8: S_ENDPGM 0, implicit [[ASHR]](<2 x s16>)
+ ; GFX9-LABEL: name: ashr_v2s16_vs
+ ; GFX9: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
+ ; GFX9: [[COPY1:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
+ ; GFX9: [[ASHR:%[0-9]+]]:vgpr(<2 x s16>) = G_ASHR [[COPY]], [[COPY1]](<2 x s16>)
+ ; GFX9: S_ENDPGM 0, implicit [[ASHR]](<2 x s16>)
+ ; GFX10-LABEL: name: ashr_v2s16_vs
+ ; GFX10: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
+ ; GFX10: [[COPY1:%[0-9]+]]:sgpr(<2 x s16>) = COPY $sgpr0
+ ; GFX10: [[ASHR:%[0-9]+]]:vgpr(<2 x s16>) = G_ASHR [[COPY]], [[COPY1]](<2 x s16>)
+ ; GFX10: S_ENDPGM 0, implicit [[ASHR]](<2 x s16>)
+ %0:vgpr(<2 x s16>) = COPY $vgpr0
+ %1:sgpr(<2 x s16>) = COPY $sgpr0
+ %2:vgpr(<2 x s16>) = G_ASHR %0, %1
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: ashr_v2s16_vv
+legalized: true
+regBankSelected: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0, $vgpr1
+ ; GFX6-LABEL: name: ashr_v2s16_vv
+ ; GFX6: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
+ ; GFX6: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr1
+ ; GFX6: [[ASHR:%[0-9]+]]:vgpr(<2 x s16>) = G_ASHR [[COPY]], [[COPY1]](<2 x s16>)
+ ; GFX6: S_ENDPGM 0, implicit [[ASHR]](<2 x s16>)
+ ; GFX7-LABEL: name: ashr_v2s16_vv
+ ; GFX7: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
+ ; GFX7: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr1
+ ; GFX7: [[ASHR:%[0-9]+]]:vgpr(<2 x s16>) = G_ASHR [[COPY]], [[COPY1]](<2 x s16>)
+ ; GFX7: S_ENDPGM 0, implicit [[ASHR]](<2 x s16>)
+ ; GFX8-LABEL: name: ashr_v2s16_vv
+ ; GFX8: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
+ ; GFX8: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr1
+ ; GFX8: [[ASHR:%[0-9]+]]:vgpr(<2 x s16>) = G_ASHR [[COPY]], [[COPY1]](<2 x s16>)
+ ; GFX8: S_ENDPGM 0, implicit [[ASHR]](<2 x s16>)
+ ; GFX9-LABEL: name: ashr_v2s16_vv
+ ; GFX9: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
+ ; GFX9: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr1
+ ; GFX9: [[ASHR:%[0-9]+]]:vgpr(<2 x s16>) = G_ASHR [[COPY]], [[COPY1]](<2 x s16>)
+ ; GFX9: S_ENDPGM 0, implicit [[ASHR]](<2 x s16>)
+ ; GFX10-LABEL: name: ashr_v2s16_vv
+ ; GFX10: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
+ ; GFX10: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr1
+ ; GFX10: [[ASHR:%[0-9]+]]:vgpr(<2 x s16>) = G_ASHR [[COPY]], [[COPY1]](<2 x s16>)
+ ; GFX10: S_ENDPGM 0, implicit [[ASHR]](<2 x s16>)
+ %0:vgpr(<2 x s16>) = COPY $vgpr0
+ %1:vgpr(<2 x s16>) = COPY $vgpr1
+ %2:vgpr(<2 x s16>) = G_ASHR %0, %1
+ S_ENDPGM 0, implicit %2
+...
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