[llvm] r366210 - AMDGPU/GlobalISel: Fix test failures in release build
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 16 07:28:31 PDT 2019
Author: arsenm
Date: Tue Jul 16 07:28:30 2019
New Revision: 366210
URL: http://llvm.org/viewvc/llvm-project?rev=366210&view=rev
Log:
AMDGPU/GlobalISel: Fix test failures in release build
Apparently the check for legal instructions during instruction
select does not happen without an asserts build, so these would
successfully select in release, and fail in debug.
Make s16 and/or/xor legal. These can just be selected directly
to the 32-bit operation, as is already done in SelectionDAG, so just
make them legal.
Modified:
llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-and.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-fcopysign.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-umax.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-umin.mir
llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp?rev=366210&r1=366209&r2=366210&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp Tue Jul 16 07:28:30 2019
@@ -291,10 +291,13 @@ bool AMDGPUInstructionSelector::selectG_
// TODO: Should this allow an SCC bank result, and produce a copy from SCC for
// the result?
if (DstRB->getID() == AMDGPU::SGPRRegBankID) {
- const TargetRegisterClass *RC
- = TRI.getConstrainedRegClassForOperand(Dst, MRI);
unsigned InstOpc = getLogicalBitOpcode(I.getOpcode(), Size > 32);
I.setDesc(TII.get(InstOpc));
+
+ const TargetRegisterClass *RC
+ = TRI.getConstrainedRegClassForOperand(Dst, MRI);
+ if (!RC)
+ return false;
return RBI.constrainGenericRegister(DstReg, *RC, MRI) &&
RBI.constrainGenericRegister(Src0.getReg(), *RC, MRI) &&
RBI.constrainGenericRegister(Src1.getReg(), *RC, MRI);
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp?rev=366210&r1=366209&r2=366210&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp Tue Jul 16 07:28:30 2019
@@ -213,7 +213,7 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo
// Report legal for any types we can handle anywhere. For the cases only legal
// on the SALU, RegBankSelect will be able to re-legalize.
getActionDefinitionsBuilder({G_AND, G_OR, G_XOR})
- .legalFor({S32, S1, S64, V2S32, V2S16, V4S16})
+ .legalFor({S32, S1, S64, V2S32, S16, V2S16, V4S16})
.clampScalar(0, S32, S64)
.moreElementsIf(isSmallOddVector(0), oneMoreElement(0))
.fewerElementsIf(vectorWiderThan(0, 32), fewerEltsToSize64Vector(0))
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-and.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-and.mir?rev=366210&r1=366209&r2=366210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-and.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-and.mir Tue Jul 16 07:28:30 2019
@@ -117,20 +117,17 @@ body: |
liveins: $sgpr0, $sgpr1
; WAVE64-LABEL: name: and_s16_sgpr_sgpr_sgpr
; WAVE64: liveins: $sgpr0, $sgpr1
- ; WAVE64: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
- ; WAVE64: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
- ; WAVE64: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
- ; WAVE64: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY1]](s32)
- ; WAVE64: [[AND:%[0-9]+]]:sgpr(s16) = G_AND [[TRUNC]], [[TRUNC1]]
- ; WAVE64: S_ENDPGM 0, implicit [[AND]](s16)
+ ; WAVE64: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; WAVE64: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1
+ ; WAVE64: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0 = S_AND_B32 [[COPY]], [[COPY1]]
+ ; WAVE64: S_ENDPGM 0, implicit [[S_AND_B32_]]
; WAVE32-LABEL: name: and_s16_sgpr_sgpr_sgpr
; WAVE32: liveins: $sgpr0, $sgpr1
- ; WAVE32: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
- ; WAVE32: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
- ; WAVE32: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
- ; WAVE32: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY1]](s32)
- ; WAVE32: [[AND:%[0-9]+]]:sgpr(s16) = G_AND [[TRUNC]], [[TRUNC1]]
- ; WAVE32: S_ENDPGM 0, implicit [[AND]](s16)
+ ; WAVE32: $vcc_hi = IMPLICIT_DEF
+ ; WAVE32: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; WAVE32: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1
+ ; WAVE32: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0 = S_AND_B32 [[COPY]], [[COPY1]]
+ ; WAVE32: S_ENDPGM 0, implicit [[S_AND_B32_]]
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = COPY $sgpr1
%2:sgpr(s16) = G_TRUNC %0
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir?rev=366210&r1=366209&r2=366210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir Tue Jul 16 07:28:30 2019
@@ -117,20 +117,17 @@ body: |
liveins: $sgpr0, $sgpr1
; WAVE64-LABEL: name: or_s16_sgpr_sgpr_sgpr
; WAVE64: liveins: $sgpr0, $sgpr1
- ; WAVE64: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
- ; WAVE64: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
- ; WAVE64: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
- ; WAVE64: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY1]](s32)
- ; WAVE64: [[OR:%[0-9]+]]:sgpr(s16) = G_OR [[TRUNC]], [[TRUNC1]]
- ; WAVE64: S_ENDPGM 0, implicit [[OR]](s16)
+ ; WAVE64: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; WAVE64: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1
+ ; WAVE64: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0 = S_OR_B32 [[COPY]], [[COPY1]]
+ ; WAVE64: S_ENDPGM 0, implicit [[S_OR_B32_]]
; WAVE32-LABEL: name: or_s16_sgpr_sgpr_sgpr
; WAVE32: liveins: $sgpr0, $sgpr1
- ; WAVE32: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
- ; WAVE32: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
- ; WAVE32: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
- ; WAVE32: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY1]](s32)
- ; WAVE32: [[OR:%[0-9]+]]:sgpr(s16) = G_OR [[TRUNC]], [[TRUNC1]]
- ; WAVE32: S_ENDPGM 0, implicit [[OR]](s16)
+ ; WAVE32: $vcc_hi = IMPLICIT_DEF
+ ; WAVE32: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; WAVE32: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1
+ ; WAVE32: [[S_OR_B32_:%[0-9]+]]:sreg_32_xm0 = S_OR_B32 [[COPY]], [[COPY1]]
+ ; WAVE32: S_ENDPGM 0, implicit [[S_OR_B32_]]
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = COPY $sgpr1
%2:sgpr(s16) = G_TRUNC %0
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir?rev=366210&r1=366209&r2=366210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir Tue Jul 16 07:28:30 2019
@@ -117,20 +117,17 @@ body: |
liveins: $sgpr0, $sgpr1
; WAVE64-LABEL: name: xor_s16_sgpr_sgpr_sgpr
; WAVE64: liveins: $sgpr0, $sgpr1
- ; WAVE64: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
- ; WAVE64: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
- ; WAVE64: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
- ; WAVE64: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY1]](s32)
- ; WAVE64: [[XOR:%[0-9]+]]:sgpr(s16) = G_XOR [[TRUNC]], [[TRUNC1]]
- ; WAVE64: S_ENDPGM 0, implicit [[XOR]](s16)
+ ; WAVE64: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; WAVE64: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1
+ ; WAVE64: [[S_XOR_B32_:%[0-9]+]]:sreg_32_xm0 = S_XOR_B32 [[COPY]], [[COPY1]]
+ ; WAVE64: S_ENDPGM 0, implicit [[S_XOR_B32_]]
; WAVE32-LABEL: name: xor_s16_sgpr_sgpr_sgpr
; WAVE32: liveins: $sgpr0, $sgpr1
- ; WAVE32: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
- ; WAVE32: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
- ; WAVE32: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
- ; WAVE32: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY1]](s32)
- ; WAVE32: [[XOR:%[0-9]+]]:sgpr(s16) = G_XOR [[TRUNC]], [[TRUNC1]]
- ; WAVE32: S_ENDPGM 0, implicit [[XOR]](s16)
+ ; WAVE32: $vcc_hi = IMPLICIT_DEF
+ ; WAVE32: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
+ ; WAVE32: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr1
+ ; WAVE32: [[S_XOR_B32_:%[0-9]+]]:sreg_32_xm0 = S_XOR_B32 [[COPY]], [[COPY1]]
+ ; WAVE32: S_ENDPGM 0, implicit [[S_XOR_B32_]]
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = COPY $sgpr1
%2:sgpr(s16) = G_TRUNC %0
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir?rev=366210&r1=366209&r2=366210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir Tue Jul 16 07:28:30 2019
@@ -156,11 +156,11 @@ body: |
; CHECK-LABEL: name: test_and_s16
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[AND]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY4]](s32)
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
+ ; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[TRUNC1]]
+ ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[AND]](s16)
+ ; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s16) = G_TRUNC %0
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir?rev=366210&r1=366209&r2=366210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir Tue Jul 16 07:28:30 2019
@@ -223,11 +223,10 @@ body: |
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]]
- ; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[AND]](s32)
- ; VI: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC]], [[TRUNC1]](s16)
+ ; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
+ ; VI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
+ ; VI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[TRUNC1]]
+ ; VI: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC]], [[AND]](s16)
; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR]](s16)
; VI: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX9-LABEL: name: test_ashr_s16_i8
@@ -235,11 +234,10 @@ body: |
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]]
- ; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[AND]](s32)
- ; GFX9: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC]], [[TRUNC1]](s16)
+ ; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
+ ; GFX9: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
+ ; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[TRUNC1]]
+ ; GFX9: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[TRUNC]], [[AND]](s16)
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR]](s16)
; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0
@@ -274,32 +272,30 @@ body: |
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]]
- ; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[AND]](s32)
+ ; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
+ ; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
+ ; VI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[TRUNC]]
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
- ; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C1]](s32)
- ; VI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; VI: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC2]], [[TRUNC1]](s16)
- ; VI: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SHL]], [[TRUNC1]](s16)
- ; VI: [[ASHR1:%[0-9]+]]:_(s16) = G_ASHR [[ASHR]], [[TRUNC]](s16)
+ ; VI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[C1]](s32)
+ ; VI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; VI: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC3]], [[TRUNC2]](s16)
+ ; VI: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SHL]], [[TRUNC2]](s16)
+ ; VI: [[ASHR1:%[0-9]+]]:_(s16) = G_ASHR [[ASHR]], [[AND]](s16)
; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR1]](s16)
; VI: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX9-LABEL: name: test_ashr_i8_i8
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]]
- ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[AND]](s32)
+ ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
+ ; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
+ ; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[TRUNC]]
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
- ; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C1]](s32)
- ; GFX9: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC2]], [[TRUNC1]](s16)
- ; GFX9: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SHL]], [[TRUNC1]](s16)
- ; GFX9: [[ASHR1:%[0-9]+]]:_(s16) = G_ASHR [[ASHR]], [[TRUNC]](s16)
+ ; GFX9: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[C1]](s32)
+ ; GFX9: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC3]], [[TRUNC2]](s16)
+ ; GFX9: [[ASHR:%[0-9]+]]:_(s16) = G_ASHR [[SHL]], [[TRUNC2]](s16)
+ ; GFX9: [[ASHR1:%[0-9]+]]:_(s16) = G_ASHR [[ASHR]], [[AND]](s16)
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASHR1]](s16)
; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-fcopysign.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-fcopysign.mir?rev=366210&r1=366209&r2=366210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-fcopysign.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-fcopysign.mir Tue Jul 16 07:28:30 2019
@@ -12,48 +12,42 @@ body: |
; SI-LABEL: name: test_copysign_s16_s16
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768
+ ; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32767
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]]
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY4]]
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[AND]](s32)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[AND1]](s32)
- ; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY5]], [[COPY6]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
- ; SI: $vgpr0 = COPY [[COPY7]](s32)
+ ; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[C1]](s32)
+ ; SI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[TRUNC2]]
+ ; SI: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[TRUNC1]]
+ ; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[AND1]]
+ ; SI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
+ ; SI: $vgpr0 = COPY [[ANYEXT]](s32)
; VI-LABEL: name: test_copysign_s16_s16
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768
+ ; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32767
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]]
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY4]]
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[AND]](s32)
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[AND1]](s32)
- ; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY5]], [[COPY6]]
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
- ; VI: $vgpr0 = COPY [[COPY7]](s32)
+ ; VI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[C1]](s32)
+ ; VI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[TRUNC2]]
+ ; VI: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[TRUNC1]]
+ ; VI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[AND1]]
+ ; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
+ ; VI: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX9-LABEL: name: test_copysign_s16_s16
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768
+ ; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32767
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]]
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY4]]
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[AND]](s32)
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[AND1]](s32)
- ; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY5]], [[COPY6]]
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
- ; GFX9: $vgpr0 = COPY [[COPY7]](s32)
+ ; GFX9: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[C1]](s32)
+ ; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[TRUNC2]]
+ ; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[TRUNC1]]
+ ; GFX9: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[AND1]]
+ ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
+ ; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s16) = G_TRUNC %0
@@ -252,57 +246,51 @@ body: |
; SI-LABEL: name: test_copysign_s16_s32
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768
+ ; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32767
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]]
+ ; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[C1]](s32)
+ ; SI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[TRUNC2]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[COPY5]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[AND]](s32)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[AND1]](s32)
- ; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY6]], [[COPY7]]
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
- ; SI: $vgpr0 = COPY [[COPY8]](s32)
+ ; SI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
+ ; SI: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC3]], [[TRUNC1]]
+ ; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[AND1]]
+ ; SI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
+ ; SI: $vgpr0 = COPY [[ANYEXT]](s32)
; VI-LABEL: name: test_copysign_s16_s32
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768
+ ; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32767
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]]
+ ; VI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[C1]](s32)
+ ; VI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[TRUNC2]]
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[COPY5]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[AND]](s32)
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[AND1]](s32)
- ; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY6]], [[COPY7]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
- ; VI: $vgpr0 = COPY [[COPY8]](s32)
+ ; VI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
+ ; VI: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC3]], [[TRUNC1]]
+ ; VI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[AND1]]
+ ; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
+ ; VI: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX9-LABEL: name: test_copysign_s16_s32
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768
+ ; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32767
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]]
+ ; GFX9: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[C1]](s32)
+ ; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[TRUNC2]]
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[COPY5]]
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[AND]](s32)
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[AND1]](s32)
- ; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY6]], [[COPY7]]
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
- ; GFX9: $vgpr0 = COPY [[COPY8]](s32)
+ ; GFX9: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
+ ; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC3]], [[TRUNC1]]
+ ; GFX9: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[AND1]]
+ ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
+ ; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s16) = G_TRUNC %0
@@ -433,60 +421,54 @@ body: |
; SI-LABEL: name: test_copysign_s16_s64
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr1_vgpr2
+ ; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768
+ ; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32767
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]]
+ ; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[C1]](s32)
+ ; SI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[TRUNC2]]
; SI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
- ; SI: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C2]](s64)
- ; SI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[TRUNC]](s32)
- ; SI: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[COPY4]]
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[AND]](s32)
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[AND1]](s32)
- ; SI: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY5]], [[COPY6]]
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
- ; SI: $vgpr0 = COPY [[COPY7]](s32)
+ ; SI: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[C2]](s64)
+ ; SI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[TRUNC3]](s32)
+ ; SI: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s64)
+ ; SI: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[TRUNC1]]
+ ; SI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[AND1]]
+ ; SI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
+ ; SI: $vgpr0 = COPY [[ANYEXT]](s32)
; VI-LABEL: name: test_copysign_s16_s64
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr1_vgpr2
+ ; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768
+ ; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32767
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]]
+ ; VI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[C1]](s32)
+ ; VI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[TRUNC2]]
; VI: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
- ; VI: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C2]](s64)
- ; VI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[TRUNC]](s32)
- ; VI: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[COPY4]]
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[AND]](s32)
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[AND1]](s32)
- ; VI: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY5]], [[COPY6]]
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
- ; VI: $vgpr0 = COPY [[COPY7]](s32)
+ ; VI: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[C2]](s64)
+ ; VI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[TRUNC3]](s32)
+ ; VI: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s64)
+ ; VI: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[TRUNC1]]
+ ; VI: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[AND1]]
+ ; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
+ ; VI: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX9-LABEL: name: test_copysign_s16_s64
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr1_vgpr2
+ ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768
+ ; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32767
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]]
+ ; GFX9: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[C1]](s32)
+ ; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[TRUNC2]]
; GFX9: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 48
- ; GFX9: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[C2]](s64)
- ; GFX9: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[TRUNC]](s32)
- ; GFX9: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[LSHR]](s64)
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[COPY4]]
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[AND]](s32)
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[AND1]](s32)
- ; GFX9: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY5]], [[COPY6]]
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
- ; GFX9: $vgpr0 = COPY [[COPY7]](s32)
+ ; GFX9: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[C2]](s64)
+ ; GFX9: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY1]], [[TRUNC3]](s32)
+ ; GFX9: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s64)
+ ; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC4]], [[TRUNC1]]
+ ; GFX9: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[AND1]]
+ ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
+ ; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s64) = COPY $vgpr1_vgpr2
%2:_(s16) = G_TRUNC %0
@@ -906,57 +888,51 @@ body: |
; SI-LABEL: name: test_copysign_s16_s32_flags
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768
+ ; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32767
- ; SI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; SI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]]
+ ; SI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[C1]](s32)
+ ; SI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[TRUNC2]]
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
- ; SI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; SI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; SI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[COPY5]]
- ; SI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[AND]](s32)
- ; SI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[AND1]](s32)
- ; SI: %14:_(s32) = nnan G_OR [[COPY6]], [[COPY7]]
- ; SI: [[COPY8:%[0-9]+]]:_(s32) = COPY %14(s32)
- ; SI: $vgpr0 = COPY [[COPY8]](s32)
+ ; SI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
+ ; SI: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC3]], [[TRUNC1]]
+ ; SI: %3:_(s16) = nnan G_OR [[AND]], [[AND1]]
+ ; SI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT %3(s16)
+ ; SI: $vgpr0 = COPY [[ANYEXT]](s32)
; VI-LABEL: name: test_copysign_s16_s32_flags
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768
+ ; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
; VI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32767
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]]
+ ; VI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[C1]](s32)
+ ; VI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[TRUNC2]]
; VI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[COPY5]]
- ; VI: [[COPY6:%[0-9]+]]:_(s32) = COPY [[AND]](s32)
- ; VI: [[COPY7:%[0-9]+]]:_(s32) = COPY [[AND1]](s32)
- ; VI: %14:_(s32) = nnan G_OR [[COPY6]], [[COPY7]]
- ; VI: [[COPY8:%[0-9]+]]:_(s32) = COPY %14(s32)
- ; VI: $vgpr0 = COPY [[COPY8]](s32)
+ ; VI: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
+ ; VI: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC3]], [[TRUNC1]]
+ ; VI: %3:_(s16) = nnan G_OR [[AND]], [[AND1]]
+ ; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT %3(s16)
+ ; VI: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX9-LABEL: name: test_copysign_s16_s32_flags
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
+ ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768
+ ; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
; GFX9: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 32767
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]]
+ ; GFX9: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[C1]](s32)
+ ; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[TRUNC2]]
; GFX9: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY1]], [[C2]](s32)
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[COPY5]]
- ; GFX9: [[COPY6:%[0-9]+]]:_(s32) = COPY [[AND]](s32)
- ; GFX9: [[COPY7:%[0-9]+]]:_(s32) = COPY [[AND1]](s32)
- ; GFX9: %14:_(s32) = nnan G_OR [[COPY6]], [[COPY7]]
- ; GFX9: [[COPY8:%[0-9]+]]:_(s32) = COPY %14(s32)
- ; GFX9: $vgpr0 = COPY [[COPY8]](s32)
+ ; GFX9: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
+ ; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC3]], [[TRUNC1]]
+ ; GFX9: %3:_(s16) = nnan G_OR [[AND]], [[AND1]]
+ ; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT %3(s16)
+ ; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s16) = G_TRUNC %0
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir?rev=366210&r1=366209&r2=366210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir Tue Jul 16 07:28:30 2019
@@ -219,11 +219,10 @@ body: |
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]]
- ; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[AND]](s32)
- ; VI: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[TRUNC1]](s16)
+ ; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
+ ; VI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
+ ; VI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[TRUNC1]]
+ ; VI: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[AND]](s16)
; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)
; VI: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX9-LABEL: name: test_lshr_s16_i8
@@ -231,11 +230,10 @@ body: |
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]]
- ; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[AND]](s32)
- ; GFX9: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[TRUNC1]](s16)
+ ; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
+ ; GFX9: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
+ ; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[TRUNC1]]
+ ; GFX9: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC]], [[AND]](s16)
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)
; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0
@@ -268,30 +266,24 @@ body: |
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]]
- ; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[AND]](s32)
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; VI: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[COPY5]]
- ; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[AND1]](s32)
- ; VI: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC1]], [[TRUNC]](s16)
+ ; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
+ ; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
+ ; VI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[TRUNC]]
+ ; VI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; VI: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[TRUNC]]
+ ; VI: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[AND1]], [[AND]](s16)
; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)
; VI: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX9-LABEL: name: test_lshr_i8_i8
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]]
- ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[AND]](s32)
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[COPY5]]
- ; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[AND1]](s32)
- ; GFX9: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[TRUNC1]], [[TRUNC]](s16)
+ ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
+ ; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
+ ; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[TRUNC]]
+ ; GFX9: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[TRUNC]]
+ ; GFX9: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[AND1]], [[AND]](s16)
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LSHR]](s16)
; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values.mir?rev=366210&r1=366209&r2=366210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values.mir Tue Jul 16 07:28:30 2019
@@ -15,53 +15,51 @@ body: |
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5
; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY $vgpr6
; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY $vgpr7
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
- ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C1]]
- ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
+ ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[TRUNC]]
+ ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+ ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C2]]
+ ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C2]]
- ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[AND]](s32)
- ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C2]]
- ; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
- ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[COPY11]]
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[OR]](s32)
- ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
- ; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C1]]
- ; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
- ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C2]]
- ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[AND3]](s32)
- ; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
- ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C2]]
- ; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[SHL1]](s32)
- ; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND5]], [[COPY15]]
- ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[OR1]](s32)
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C3]]
+ ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[AND1]](s32)
+ ; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
+ ; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC2]]
+ ; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32)
+ ; CHECK: [[AND3:%[0-9]+]]:_(s16) = G_AND [[TRUNC3]], [[TRUNC]]
; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
- ; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C1]]
- ; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY5]](s32)
- ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C2]]
- ; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[AND6]](s32)
- ; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY4]](s32)
- ; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY18]], [[C2]]
- ; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[SHL2]](s32)
- ; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[COPY19]]
- ; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[OR2]](s32)
+ ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
+ ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C2]]
+ ; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[COPY3]](s32)
+ ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C3]]
+ ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[AND4]](s32)
+ ; CHECK: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
+ ; CHECK: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND3]], [[TRUNC4]]
+ ; CHECK: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[COPY4]](s32)
+ ; CHECK: [[AND6:%[0-9]+]]:_(s16) = G_AND [[TRUNC5]], [[TRUNC]]
; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
- ; CHECK: [[COPY20:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
- ; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY20]], [[C1]]
- ; CHECK: [[COPY21:%[0-9]+]]:_(s32) = COPY [[COPY7]](s32)
- ; CHECK: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C2]]
- ; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[AND9]](s32)
- ; CHECK: [[COPY22:%[0-9]+]]:_(s32) = COPY [[COPY6]](s32)
- ; CHECK: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY22]], [[C2]]
- ; CHECK: [[COPY23:%[0-9]+]]:_(s32) = COPY [[SHL3]](s32)
- ; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND11]], [[COPY23]]
- ; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[OR3]](s32)
- ; CHECK: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[TRUNC]](s16), [[TRUNC1]](s16), [[TRUNC2]](s16), [[TRUNC3]](s16)
+ ; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
+ ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C2]]
+ ; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[COPY5]](s32)
+ ; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C3]]
+ ; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[AND7]](s32)
+ ; CHECK: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
+ ; CHECK: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[TRUNC6]]
+ ; CHECK: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[COPY6]](s32)
+ ; CHECK: [[AND9:%[0-9]+]]:_(s16) = G_AND [[TRUNC7]], [[TRUNC]]
+ ; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+ ; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
+ ; CHECK: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C2]]
+ ; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY7]](s32)
+ ; CHECK: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY15]], [[C3]]
+ ; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[AND10]](s32)
+ ; CHECK: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
+ ; CHECK: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND9]], [[TRUNC8]]
+ ; CHECK: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[OR]](s16), [[OR1]](s16), [[OR2]](s16), [[OR3]](s16)
; CHECK: $vgpr0_vgpr1 = COPY [[MV]](p1)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
@@ -91,20 +89,22 @@ body: |
; CHECK-LABEL: name: test_merge_s16_s8_s8
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
- ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C3]]
- ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C2]](s32)
+ ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
+ ; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[TRUNC]]
+ ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+ ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C4]]
+ ; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C4]]
- ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[AND]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C4]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
- ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[COPY3]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY4]](s32)
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C5]]
+ ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[AND1]](s32)
+ ; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
+ ; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC2]]
+ ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
+ ; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s8) = G_CONSTANT i8 0
%1:_(s8) = G_CONSTANT i8 1
%2:_(s16) = G_MERGE_VALUES %0, %1
@@ -160,31 +160,31 @@ body: |
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 3
- ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
- ; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C5]]
- ; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C4]](s32)
+ ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
+ ; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[TRUNC]]
+ ; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+ ; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C6]]
+ ; CHECK: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C6]]
- ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[AND]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C6]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
- ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[COPY3]]
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[OR]](s32)
- ; CHECK: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C7]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C5]]
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
- ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C6]]
- ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[AND3]](s32)
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C6]]
- ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SHL1]](s32)
- ; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND5]], [[COPY7]]
- ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[OR1]](s32)
- ; CHECK: [[MV:%[0-9]+]]:_(s32) = G_MERGE_VALUES [[TRUNC]](s16), [[TRUNC1]](s16)
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C7]]
+ ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[AND1]](s32)
+ ; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
+ ; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC2]]
+ ; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[C2]](s32)
+ ; CHECK: [[AND3:%[0-9]+]]:_(s16) = G_AND [[TRUNC3]], [[TRUNC]]
+ ; CHECK: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
+ ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C6]]
+ ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+ ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C7]]
+ ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[AND4]](s32)
+ ; CHECK: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
+ ; CHECK: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND3]], [[TRUNC4]]
+ ; CHECK: [[MV:%[0-9]+]]:_(s32) = G_MERGE_VALUES [[OR]](s16), [[OR1]](s16)
; CHECK: $vgpr0 = COPY [[MV]](s32)
%0:_(s8) = G_CONSTANT i8 0
%1:_(s8) = G_CONSTANT i8 1
@@ -424,75 +424,71 @@ body: |
; CHECK: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 9
; CHECK: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; CHECK: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 11
- ; CHECK: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
- ; CHECK: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C12]](s32)
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C13]]
- ; CHECK: [[C14:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C12]](s32)
+ ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
+ ; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[TRUNC]]
+ ; CHECK: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+ ; CHECK: [[C14:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C13]](s32)
+ ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C14]]
+ ; CHECK: [[C15:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C14]]
- ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[AND]](s32)
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C14]]
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[SHL]](s32)
- ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND2]], [[COPY3]]
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[OR]](s32)
- ; CHECK: [[C15:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C15]](s32)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C13]]
- ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
- ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C14]]
- ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND4]], [[AND3]](s32)
- ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C2]](s32)
- ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C14]]
- ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[SHL1]](s32)
- ; CHECK: [[OR1:%[0-9]+]]:_(s32) = G_OR [[AND5]], [[COPY7]]
- ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[OR1]](s32)
+ ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C15]]
+ ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND2]], [[AND1]](s32)
+ ; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[SHL]](s32)
+ ; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[AND]], [[TRUNC2]]
+ ; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[C2]](s32)
+ ; CHECK: [[AND3:%[0-9]+]]:_(s16) = G_AND [[TRUNC3]], [[TRUNC]]
; CHECK: [[C16:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
- ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C16]](s32)
- ; CHECK: [[AND6:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C13]]
- ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
- ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C14]]
- ; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND7]], [[AND6]](s32)
- ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C4]](s32)
- ; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C14]]
- ; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[SHL2]](s32)
- ; CHECK: [[OR2:%[0-9]+]]:_(s32) = G_OR [[AND8]], [[COPY11]]
- ; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[OR2]](s32)
+ ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[C16]](s32)
+ ; CHECK: [[AND4:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C14]]
+ ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+ ; CHECK: [[AND5:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C15]]
+ ; CHECK: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[AND5]], [[AND4]](s32)
+ ; CHECK: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[SHL1]](s32)
+ ; CHECK: [[OR1:%[0-9]+]]:_(s16) = G_OR [[AND3]], [[TRUNC4]]
+ ; CHECK: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[C4]](s32)
+ ; CHECK: [[AND6:%[0-9]+]]:_(s16) = G_AND [[TRUNC5]], [[TRUNC]]
; CHECK: [[C17:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
- ; CHECK: [[COPY12:%[0-9]+]]:_(s32) = COPY [[C17]](s32)
- ; CHECK: [[AND9:%[0-9]+]]:_(s32) = G_AND [[COPY12]], [[C13]]
- ; CHECK: [[COPY13:%[0-9]+]]:_(s32) = COPY [[C7]](s32)
- ; CHECK: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY13]], [[C14]]
- ; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND10]], [[AND9]](s32)
- ; CHECK: [[COPY14:%[0-9]+]]:_(s32) = COPY [[C6]](s32)
- ; CHECK: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY14]], [[C14]]
- ; CHECK: [[COPY15:%[0-9]+]]:_(s32) = COPY [[SHL3]](s32)
- ; CHECK: [[OR3:%[0-9]+]]:_(s32) = G_OR [[AND11]], [[COPY15]]
- ; CHECK: [[TRUNC3:%[0-9]+]]:_(s16) = G_TRUNC [[OR3]](s32)
+ ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[C17]](s32)
+ ; CHECK: [[AND7:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C14]]
+ ; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[C5]](s32)
+ ; CHECK: [[AND8:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C15]]
+ ; CHECK: [[SHL2:%[0-9]+]]:_(s32) = G_SHL [[AND8]], [[AND7]](s32)
+ ; CHECK: [[TRUNC6:%[0-9]+]]:_(s16) = G_TRUNC [[SHL2]](s32)
+ ; CHECK: [[OR2:%[0-9]+]]:_(s16) = G_OR [[AND6]], [[TRUNC6]]
+ ; CHECK: [[TRUNC7:%[0-9]+]]:_(s16) = G_TRUNC [[C6]](s32)
+ ; CHECK: [[AND9:%[0-9]+]]:_(s16) = G_AND [[TRUNC7]], [[TRUNC]]
; CHECK: [[C18:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
- ; CHECK: [[COPY16:%[0-9]+]]:_(s32) = COPY [[C18]](s32)
- ; CHECK: [[AND12:%[0-9]+]]:_(s32) = G_AND [[COPY16]], [[C13]]
- ; CHECK: [[COPY17:%[0-9]+]]:_(s32) = COPY [[C9]](s32)
- ; CHECK: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY17]], [[C14]]
- ; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND13]], [[AND12]](s32)
- ; CHECK: [[COPY18:%[0-9]+]]:_(s32) = COPY [[C8]](s32)
- ; CHECK: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY18]], [[C14]]
- ; CHECK: [[COPY19:%[0-9]+]]:_(s32) = COPY [[SHL4]](s32)
- ; CHECK: [[OR4:%[0-9]+]]:_(s32) = G_OR [[AND14]], [[COPY19]]
- ; CHECK: [[TRUNC4:%[0-9]+]]:_(s16) = G_TRUNC [[OR4]](s32)
+ ; CHECK: [[COPY6:%[0-9]+]]:_(s32) = COPY [[C18]](s32)
+ ; CHECK: [[AND10:%[0-9]+]]:_(s32) = G_AND [[COPY6]], [[C14]]
+ ; CHECK: [[COPY7:%[0-9]+]]:_(s32) = COPY [[C7]](s32)
+ ; CHECK: [[AND11:%[0-9]+]]:_(s32) = G_AND [[COPY7]], [[C15]]
+ ; CHECK: [[SHL3:%[0-9]+]]:_(s32) = G_SHL [[AND11]], [[AND10]](s32)
+ ; CHECK: [[TRUNC8:%[0-9]+]]:_(s16) = G_TRUNC [[SHL3]](s32)
+ ; CHECK: [[OR3:%[0-9]+]]:_(s16) = G_OR [[AND9]], [[TRUNC8]]
+ ; CHECK: [[TRUNC9:%[0-9]+]]:_(s16) = G_TRUNC [[C8]](s32)
+ ; CHECK: [[AND12:%[0-9]+]]:_(s16) = G_AND [[TRUNC9]], [[TRUNC]]
; CHECK: [[C19:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
- ; CHECK: [[COPY20:%[0-9]+]]:_(s32) = COPY [[C19]](s32)
- ; CHECK: [[AND15:%[0-9]+]]:_(s32) = G_AND [[COPY20]], [[C13]]
- ; CHECK: [[COPY21:%[0-9]+]]:_(s32) = COPY [[C11]](s32)
- ; CHECK: [[AND16:%[0-9]+]]:_(s32) = G_AND [[COPY21]], [[C14]]
- ; CHECK: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND16]], [[AND15]](s32)
- ; CHECK: [[COPY22:%[0-9]+]]:_(s32) = COPY [[C10]](s32)
- ; CHECK: [[AND17:%[0-9]+]]:_(s32) = G_AND [[COPY22]], [[C14]]
- ; CHECK: [[COPY23:%[0-9]+]]:_(s32) = COPY [[SHL5]](s32)
- ; CHECK: [[OR5:%[0-9]+]]:_(s32) = G_OR [[AND17]], [[COPY23]]
- ; CHECK: [[TRUNC5:%[0-9]+]]:_(s16) = G_TRUNC [[OR5]](s32)
- ; CHECK: [[MV:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[TRUNC]](s16), [[TRUNC1]](s16), [[TRUNC2]](s16), [[TRUNC3]](s16), [[TRUNC4]](s16), [[TRUNC5]](s16)
+ ; CHECK: [[COPY8:%[0-9]+]]:_(s32) = COPY [[C19]](s32)
+ ; CHECK: [[AND13:%[0-9]+]]:_(s32) = G_AND [[COPY8]], [[C14]]
+ ; CHECK: [[COPY9:%[0-9]+]]:_(s32) = COPY [[C9]](s32)
+ ; CHECK: [[AND14:%[0-9]+]]:_(s32) = G_AND [[COPY9]], [[C15]]
+ ; CHECK: [[SHL4:%[0-9]+]]:_(s32) = G_SHL [[AND14]], [[AND13]](s32)
+ ; CHECK: [[TRUNC10:%[0-9]+]]:_(s16) = G_TRUNC [[SHL4]](s32)
+ ; CHECK: [[OR4:%[0-9]+]]:_(s16) = G_OR [[AND12]], [[TRUNC10]]
+ ; CHECK: [[TRUNC11:%[0-9]+]]:_(s16) = G_TRUNC [[C10]](s32)
+ ; CHECK: [[AND15:%[0-9]+]]:_(s16) = G_AND [[TRUNC11]], [[TRUNC]]
+ ; CHECK: [[C20:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
+ ; CHECK: [[COPY10:%[0-9]+]]:_(s32) = COPY [[C20]](s32)
+ ; CHECK: [[AND16:%[0-9]+]]:_(s32) = G_AND [[COPY10]], [[C14]]
+ ; CHECK: [[COPY11:%[0-9]+]]:_(s32) = COPY [[C11]](s32)
+ ; CHECK: [[AND17:%[0-9]+]]:_(s32) = G_AND [[COPY11]], [[C15]]
+ ; CHECK: [[SHL5:%[0-9]+]]:_(s32) = G_SHL [[AND17]], [[AND16]](s32)
+ ; CHECK: [[TRUNC12:%[0-9]+]]:_(s16) = G_TRUNC [[SHL5]](s32)
+ ; CHECK: [[OR5:%[0-9]+]]:_(s16) = G_OR [[AND15]], [[TRUNC12]]
+ ; CHECK: [[MV:%[0-9]+]]:_(s96) = G_MERGE_VALUES [[OR]](s16), [[OR1]](s16), [[OR2]](s16), [[OR3]](s16), [[OR4]](s16), [[OR5]](s16)
; CHECK: $vgpr0_vgpr1_vgpr2 = COPY [[MV]](s96)
%0:_(s8) = G_CONSTANT i8 0
%1:_(s8) = G_CONSTANT i8 1
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir?rev=366210&r1=366209&r2=366210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir Tue Jul 16 07:28:30 2019
@@ -156,11 +156,11 @@ body: |
; CHECK-LABEL: name: test_or_s16
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY2]], [[COPY3]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY4]](s32)
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
+ ; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[TRUNC]], [[TRUNC1]]
+ ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
+ ; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s16) = G_TRUNC %0
@@ -179,11 +179,11 @@ body: |
; CHECK-LABEL: name: test_or_s24
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY2]], [[COPY3]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY4]](s32)
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
+ ; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[TRUNC]], [[TRUNC1]]
+ ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
+ ; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s16) = G_TRUNC %0
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir?rev=366210&r1=366209&r2=366210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir Tue Jul 16 07:28:30 2019
@@ -214,11 +214,10 @@ body: |
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]]
- ; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[AND]](s32)
- ; VI: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[TRUNC1]](s16)
+ ; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
+ ; VI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
+ ; VI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[TRUNC1]]
+ ; VI: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[AND]](s16)
; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL]](s16)
; VI: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX9-LABEL: name: test_shl_s16_i8
@@ -226,11 +225,10 @@ body: |
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]]
- ; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[AND]](s32)
- ; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[TRUNC1]](s16)
+ ; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
+ ; GFX9: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
+ ; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[TRUNC1]]
+ ; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC]], [[AND]](s16)
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL]](s16)
; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0
@@ -262,24 +260,22 @@ body: |
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]]
- ; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[AND]](s32)
- ; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; VI: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[TRUNC]](s16)
+ ; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
+ ; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
+ ; VI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[TRUNC]]
+ ; VI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; VI: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC2]], [[AND]](s16)
; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL]](s16)
; VI: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX9-LABEL: name: test_shl_i8_i8
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]]
- ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[AND]](s32)
- ; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[TRUNC]](s16)
+ ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
+ ; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
+ ; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[TRUNC]]
+ ; GFX9: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC2]], [[AND]](s16)
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL]](s16)
; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0
@@ -715,24 +711,22 @@ body: |
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]]
- ; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[AND]](s32)
- ; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; VI: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[TRUNC]](s16)
+ ; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
+ ; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
+ ; VI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[TRUNC]]
+ ; VI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; VI: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC2]], [[AND]](s16)
; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL]](s16)
; VI: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX9-LABEL: name: test_shl_s7_s7
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]]
- ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[AND]](s32)
- ; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
- ; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC1]], [[TRUNC]](s16)
+ ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
+ ; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
+ ; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[TRUNC]]
+ ; GFX9: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX9: [[SHL:%[0-9]+]]:_(s16) = G_SHL [[TRUNC2]], [[AND]](s16)
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[SHL]](s16)
; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-umax.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-umax.mir?rev=366210&r1=366209&r2=366210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-umax.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-umax.mir Tue Jul 16 07:28:30 2019
@@ -93,28 +93,24 @@ body: |
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]]
- ; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[AND]](s32)
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[COPY3]]
- ; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[AND1]](s32)
- ; VI: [[UMAX:%[0-9]+]]:_(s16) = G_UMAX [[TRUNC]], [[TRUNC1]]
+ ; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
+ ; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; VI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[TRUNC]]
+ ; VI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
+ ; VI: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[TRUNC]]
+ ; VI: [[UMAX:%[0-9]+]]:_(s16) = G_UMAX [[AND]], [[AND1]]
; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UMAX]](s16)
; VI: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX9-LABEL: name: test_umax_s8
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]]
- ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[AND]](s32)
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[COPY3]]
- ; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[AND1]](s32)
- ; GFX9: [[UMAX:%[0-9]+]]:_(s16) = G_UMAX [[TRUNC]], [[TRUNC1]]
+ ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
+ ; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[TRUNC]]
+ ; GFX9: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
+ ; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[TRUNC]]
+ ; GFX9: [[UMAX:%[0-9]+]]:_(s16) = G_UMAX [[AND]], [[AND1]]
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UMAX]](s16)
; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-umin.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-umin.mir?rev=366210&r1=366209&r2=366210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-umin.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-umin.mir Tue Jul 16 07:28:30 2019
@@ -93,28 +93,24 @@ body: |
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; VI: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; VI: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; VI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]]
- ; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[AND]](s32)
- ; VI: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; VI: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[COPY3]]
- ; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[AND1]](s32)
- ; VI: [[UMIN:%[0-9]+]]:_(s16) = G_UMIN [[TRUNC]], [[TRUNC1]]
+ ; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
+ ; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; VI: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[TRUNC]]
+ ; VI: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
+ ; VI: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[TRUNC]]
+ ; VI: [[UMIN:%[0-9]+]]:_(s16) = G_UMIN [[AND]], [[AND1]]
; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UMIN]](s16)
; VI: $vgpr0 = COPY [[ANYEXT]](s32)
; GFX9-LABEL: name: test_umin_s8
; GFX9: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; GFX9: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; GFX9: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; GFX9: [[COPY3:%[0-9]+]]:_(s32) = COPY [[C]](s32)
- ; GFX9: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[COPY3]]
- ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[AND]](s32)
- ; GFX9: [[COPY4:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; GFX9: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[COPY3]]
- ; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[AND1]](s32)
- ; GFX9: [[UMIN:%[0-9]+]]:_(s16) = G_UMIN [[TRUNC]], [[TRUNC1]]
+ ; GFX9: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[C]](s32)
+ ; GFX9: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX9: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC1]], [[TRUNC]]
+ ; GFX9: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
+ ; GFX9: [[AND1:%[0-9]+]]:_(s16) = G_AND [[TRUNC2]], [[TRUNC]]
+ ; GFX9: [[UMIN:%[0-9]+]]:_(s16) = G_UMIN [[AND]], [[AND1]]
; GFX9: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UMIN]](s16)
; GFX9: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0
Modified: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir?rev=366210&r1=366209&r2=366210&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir Tue Jul 16 07:28:30 2019
@@ -156,11 +156,11 @@ body: |
; CHECK-LABEL: name: test_xor_s16
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY2]], [[COPY3]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[XOR]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY4]](s32)
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
+ ; CHECK: [[XOR:%[0-9]+]]:_(s16) = G_XOR [[TRUNC]], [[TRUNC1]]
+ ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[XOR]](s16)
+ ; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s16) = G_TRUNC %0
@@ -179,11 +179,11 @@ body: |
; CHECK-LABEL: name: test_xor_s24
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
- ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
- ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
- ; CHECK: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY2]], [[COPY3]]
- ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[XOR]](s32)
- ; CHECK: $vgpr0 = COPY [[COPY4]](s32)
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
+ ; CHECK: [[XOR:%[0-9]+]]:_(s16) = G_XOR [[TRUNC]], [[TRUNC1]]
+ ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[XOR]](s16)
+ ; CHECK: $vgpr0 = COPY [[ANYEXT]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s16) = G_TRUNC %0
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