[PATCH] D64760: [x86] use more phadd for reductions

[Sanjay Patel via Phabricator via llvm-commits]

spatel created this revision.
spatel added reviewers: RKSimon, craig.topper.
Herald added subscribers: hiraditya, mcrosier.
Herald added a project: LLVM.

This is part of what is requested by PR42023:
https://bugs.llvm.org/show_bug.cgi?id=42023

There's an extension needed for FP add, but exactly how we would specify that using flags is not clear to me, so I left that as a TODO.
We're still missing patterns for partial reductions when the input vector is 256-bit or 512-bit, but I think that's a failure of vector narrowing. If we can reduce the widths, then this matching should work on those tests.


https://reviews.llvm.org/D64760

Files:
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/test/CodeGen/X86/phaddsub-extract.ll
  llvm/test/CodeGen/X86/vector-reduce-add-widen.ll
  llvm/test/CodeGen/X86/vector-reduce-add.ll

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