[PATCH] D64616: [ARM][LowOverheadLoops] Fix branch target codegen

[Sam Parker via Phabricator via llvm-commits]

samparker marked an inline comment as done.
samparker added inline comments.


================
Comment at: lib/Target/ARM/ARMISelLowering.cpp:13076
 
-  unsigned IntOp = cast<ConstantSDNode>(Int.getOperand(1))->getZExtValue();
-  if (IntOp != Intrinsic::test_set_loop_iterations)
-    return SDValue();
+  assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
+         "unexpected condition code");
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SjoerdMeijer wrote:
> Silly question: can you remind me why we are only looking at EQ and NE? 
> In tests only these 2 conditions are used. Does it make sense to test others as well, see what happens?
Yeah, for loop decrement that could happen... I'll add some more tests.


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  https://reviews.llvm.org/D64616/new/

https://reviews.llvm.org/D64616