[PATCH] D64220: [PowerPC] Remove redundant load immediate instructions

[Qing Shan Zhang via Phabricator via llvm-commits]

steven.zhang added inline comments.


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Comment at: llvm/test/CodeGen/PowerPC/remove-redundant-load-imm.mir:5
+---
+name:            t1
+alignment:       4
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nemanjai wrote:
> steven.zhang wrote:
> > Could you show me the LLVM IR that produce these two redundant LI ? So that, we could figure out if they can be avoided instead of removing it in the peephole.
> More or less any IR that has multiple PHI nodes that have a zero coming in from the same block and the register has to be spilled.
> Perhaps we should add a test case such as that (with an inline asm call that clobbers registers thereby requiring spills).
Yeah, at least one case to indicate the scenario that produce this pattern,


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  https://reviews.llvm.org/D64220/new/

https://reviews.llvm.org/D64220