[PATCH] D64510: AMDGPU: Don't rely on m0 being -1 for GWS offsets

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added reviewers: rampitec, b-sumner.
Herald added subscribers: t-tye, tpr, dstuttard, yaxunl, nhaehnle, wdng, jvesely, kzhuravl.

This only works if the high bits of m0 are also 0, so m0 would have to
be set to 0xffff.


https://reviews.llvm.org/D64510

Files:
  lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
  test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.init.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.br.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.p.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.release.all.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.v.ll

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