[PATCH] D64503: LiveIntervals: Fix handleMove asserting on BUNDLE

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added reviewers: qcolombet, MatzeB.
Herald added subscribers: javed.absar, nhaehnle, wdng, jvesely.

The top-level BUNDLE instruction should behave as an ordinary
instruction. It is supposed to have all relevant registers as implicit
operands. Moving it should work as any other instruction. I believe
the assert intended to avoid moving instructions inside bundles.


https://reviews.llvm.org/D64503

Files:
  lib/CodeGen/LiveIntervals.cpp
  test/CodeGen/AMDGPU/scheduler-handle-move-bundle.mir


Index: test/CodeGen/AMDGPU/scheduler-handle-move-bundle.mir
===================================================================
--- /dev/null
+++ test/CodeGen/AMDGPU/scheduler-handle-move-bundle.mir
@@ -0,0 +1,52 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -run-pass=machine-scheduler -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
+
+# handleMove was called for the BUNDLE pseudo-instruction, but
+# considered it to be an instruction in the bundle. Make sure it
+# doesn't assert when the whole bundle is moved.
+
+---
+name: handleMove_bundle
+tracksRegLiveness: true
+machineFunctionInfo:
+  isEntryFunction: true
+  memoryBound:     false
+  waveLimiter:     false
+body:             |
+  bb.0:
+    liveins: $sgpr4_sgpr5
+
+    ; GCN-LABEL: name: handleMove_bundle
+    ; GCN: liveins: $sgpr4_sgpr5
+    ; GCN: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
+    ; GCN: $vcc_hi = IMPLICIT_DEF
+    ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
+    ; GCN: [[S_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[COPY]], 0, 0, 0 :: (dereferenceable invariant load 4, align 16, addrspace 4)
+    ; GCN: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    ; GCN: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 2, implicit $exec
+    ; GCN: DS_WRITE_B32_gfx9 [[V_MOV_B32_e32_1]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: (store 4, addrspace 3)
+    ; GCN: $m0 = S_MOV_B32 0
+    ; GCN: $vgpr0 = COPY [[S_LOAD_DWORD_IMM]]
+    ; GCN: BUNDLE implicit $vgpr0, implicit $m0, implicit $exec {
+    ; GCN:   DS_GWS_INIT $vgpr0, 11, 0, implicit $m0, implicit $exec :: (store 4)
+    ; GCN:   S_WAITCNT 0
+    ; GCN: }
+    ; GCN: DS_WRITE_B32_gfx9 [[V_MOV_B32_e32_1]], [[V_MOV_B32_e32_2]], 0, 0, implicit $exec :: (store 4, addrspace 3)
+    ; GCN: S_ENDPGM 0
+    $vcc_hi = IMPLICIT_DEF
+    %2:sgpr_64 = COPY $sgpr4_sgpr5
+    %5:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %2, 0, 0, 0 :: (dereferenceable invariant load 4, align 16, addrspace 4)
+    %6:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
+    %7:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    DS_WRITE_B32_gfx9 %7, %6, 0, 0, implicit $exec :: (store 4, addrspace 3)
+    $m0 = S_MOV_B32 0
+    $vgpr0 = COPY %5
+    BUNDLE implicit killed $vgpr0, implicit $m0, implicit $exec {
+      DS_GWS_INIT $vgpr0, 11, 0, implicit $m0, implicit $exec :: (store 4)
+      S_WAITCNT 0
+    }
+    %8:vgpr_32 = V_MOV_B32_e32 2, implicit $exec
+    DS_WRITE_B32_gfx9 %7, %8, 0, 0, implicit $exec :: (store 4, addrspace 3)
+    S_ENDPGM 0
+
+...
Index: lib/CodeGen/LiveIntervals.cpp
===================================================================
--- lib/CodeGen/LiveIntervals.cpp
+++ lib/CodeGen/LiveIntervals.cpp
@@ -1439,7 +1439,8 @@
 };
 
 void LiveIntervals::handleMove(MachineInstr &MI, bool UpdateFlags) {
-  assert(!MI.isBundled() && "Can't handle bundled instructions yet.");
+  assert((!MI.isBundled() || MI.getOpcode() == TargetOpcode::BUNDLE) &&
+         "Cannot move instruction in bundle");
   SlotIndex OldIndex = Indexes->getInstructionIndex(MI);
   Indexes->removeMachineInstrFromMaps(MI);
   SlotIndex NewIndex = Indexes->insertMachineInstrInMaps(MI);


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