[llvm] r365641 - [NFC][InstCombine] Redundant masking before left-shift (PR42563)
Roman Lebedev via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 10 08:08:06 PDT 2019
Author: lebedevri
Date: Wed Jul 10 08:08:06 2019
New Revision: 365641
URL: http://llvm.org/viewvc/llvm-project?rev=365641&view=rev
Log:
[NFC][InstCombine] Redundant masking before left-shift (PR42563)
alive proofs:
a,b: https://rise4fun.com/Alive/4zsf
c,d,e,f: https://rise4fun.com/Alive/RC49
Indeed, not all of these patterns are canonical.
But since this fold will only produce a single instruction
i'm really interested in handling even uncanonical patterns.
Other than these 6 patterns, i can't think of any other
reasonable variants right now, although i'm sure they exist.
For now let's start with patterns where both shift amounts are variable,
with trivial constant "offset" between them, since i believe this is
both simplest to handle and i think this is most common.
But again, there are likely other variants where we could use
ValueTracking/ConstantRange to handle more cases.
https://bugs.llvm.org/show_bug.cgi?id=42563
Added:
llvm/trunk/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-a.ll
llvm/trunk/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-b.ll
llvm/trunk/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-c.ll
llvm/trunk/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-d.ll
llvm/trunk/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-e.ll
llvm/trunk/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-f.ll
llvm/trunk/test/Transforms/InstCombine/redundant-right-shift-input-masking.ll
Removed:
llvm/trunk/test/Transforms/InstCombine/redundant-shift-input-masking.ll
Added: llvm/trunk/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-a.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-a.ll?rev=365641&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-a.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-a.ll Wed Jul 10 08:08:06 2019
@@ -0,0 +1,432 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt %s -instcombine -S | FileCheck %s
+
+; If we have some pattern that leaves only some low bits set, and then performs
+; left-shift of those bits, if none of the bits that are left after the final
+; shift are modified by the mask, we can omit the mask.
+
+; There are many variants to this pattern:
+; a) (x & ((1 << maskNbits) - 1)) << shiftNbits
+; simplify to:
+; x << shiftNbits
+; iff (maskNbits+shiftNbits) u>= bitwidth(x)
+
+; Simple tests. We don't care about extra uses.
+
+declare void @use32(i32)
+
+define i32 @t0_basic(i32 %x, i32 %nbits) {
+; CHECK-LABEL: @t0_basic(
+; CHECK-NEXT: [[T0:%.*]] = shl i32 1, [[NBITS:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = add nsw i32 [[T0]], -1
+; CHECK-NEXT: [[T2:%.*]] = and i32 [[T1]], [[X:%.*]]
+; CHECK-NEXT: [[T3:%.*]] = sub i32 32, [[NBITS]]
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: call void @use32(i32 [[T2]])
+; CHECK-NEXT: call void @use32(i32 [[T3]])
+; CHECK-NEXT: [[T4:%.*]] = shl i32 [[T2]], [[T3]]
+; CHECK-NEXT: ret i32 [[T4]]
+;
+ %t0 = shl i32 1, %nbits
+ %t1 = add nsw i32 %t0, -1
+ %t2 = and i32 %t1, %x
+ %t3 = sub i32 32, %nbits
+ call void @use32(i32 %t0)
+ call void @use32(i32 %t1)
+ call void @use32(i32 %t2)
+ call void @use32(i32 %t3)
+ %t4 = shl i32 %t2, %t3
+ ret i32 %t4
+}
+
+define i32 @t1_bigger_shift(i32 %x, i32 %nbits) {
+; CHECK-LABEL: @t1_bigger_shift(
+; CHECK-NEXT: [[T0:%.*]] = shl i32 1, [[NBITS:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = add nsw i32 [[T0]], -1
+; CHECK-NEXT: [[T2:%.*]] = and i32 [[T1]], [[X:%.*]]
+; CHECK-NEXT: [[T3:%.*]] = sub i32 33, [[NBITS]]
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: call void @use32(i32 [[T2]])
+; CHECK-NEXT: call void @use32(i32 [[T3]])
+; CHECK-NEXT: [[T4:%.*]] = shl i32 [[T2]], [[T3]]
+; CHECK-NEXT: ret i32 [[T4]]
+;
+ %t0 = shl i32 1, %nbits
+ %t1 = add nsw i32 %t0, -1
+ %t2 = and i32 %t1, %x
+ %t3 = sub i32 33, %nbits ; subtracting from bitwidth+1
+ call void @use32(i32 %t0)
+ call void @use32(i32 %t1)
+ call void @use32(i32 %t2)
+ call void @use32(i32 %t3)
+ %t4 = shl i32 %t2, %t3
+ ret i32 %t4
+}
+
+define i32 @t2_bigger_mask(i32 %x, i32 %nbits) {
+; CHECK-LABEL: @t2_bigger_mask(
+; CHECK-NEXT: [[T0:%.*]] = add i32 [[NBITS:%.*]], 1
+; CHECK-NEXT: [[T1:%.*]] = shl i32 1, [[T0]]
+; CHECK-NEXT: [[T2:%.*]] = add nsw i32 [[T1]], -1
+; CHECK-NEXT: [[T3:%.*]] = and i32 [[T2]], [[X:%.*]]
+; CHECK-NEXT: [[T4:%.*]] = sub i32 32, [[NBITS]]
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: call void @use32(i32 [[T2]])
+; CHECK-NEXT: call void @use32(i32 [[T3]])
+; CHECK-NEXT: call void @use32(i32 [[T4]])
+; CHECK-NEXT: [[T5:%.*]] = shl i32 [[T3]], [[T4]]
+; CHECK-NEXT: ret i32 [[T5]]
+;
+ %t0 = add i32 %nbits, 1
+ %t1 = shl i32 1, %t0 ; shifting by nbits+1
+ %t2 = add nsw i32 %t1, -1
+ %t3 = and i32 %t2, %x
+ %t4 = sub i32 32, %nbits
+ call void @use32(i32 %t0)
+ call void @use32(i32 %t1)
+ call void @use32(i32 %t2)
+ call void @use32(i32 %t3)
+ call void @use32(i32 %t4)
+ %t5 = shl i32 %t3, %t4
+ ret i32 %t5
+}
+
+; Vectors
+
+declare void @use3xi32(<3 x i32>)
+
+define <3 x i32> @t3_vec_splat(<3 x i32> %x, <3 x i32> %nbits) {
+; CHECK-LABEL: @t3_vec_splat(
+; CHECK-NEXT: [[T1:%.*]] = shl <3 x i32> <i32 1, i32 1, i32 1>, [[NBITS:%.*]]
+; CHECK-NEXT: [[T2:%.*]] = add nsw <3 x i32> [[T1]], <i32 -1, i32 -1, i32 -1>
+; CHECK-NEXT: [[T3:%.*]] = and <3 x i32> [[T2]], [[X:%.*]]
+; CHECK-NEXT: [[T4:%.*]] = sub <3 x i32> <i32 32, i32 32, i32 32>, [[NBITS]]
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[NBITS]])
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T1]])
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T2]])
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T3]])
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T4]])
+; CHECK-NEXT: [[T5:%.*]] = shl <3 x i32> [[T3]], [[T4]]
+; CHECK-NEXT: ret <3 x i32> [[T5]]
+;
+ %t0 = add <3 x i32> %nbits, <i32 0, i32 0, i32 0>
+ %t1 = shl <3 x i32> <i32 1, i32 1, i32 1>, %t0
+ %t2 = add nsw <3 x i32> %t1, <i32 -1, i32 -1, i32 -1>
+ %t3 = and <3 x i32> %t2, %x
+ %t4 = sub <3 x i32> <i32 32, i32 32, i32 32>, %nbits
+ call void @use3xi32(<3 x i32> %t0)
+ call void @use3xi32(<3 x i32> %t1)
+ call void @use3xi32(<3 x i32> %t2)
+ call void @use3xi32(<3 x i32> %t3)
+ call void @use3xi32(<3 x i32> %t4)
+ %t5 = shl <3 x i32> %t3, %t4
+ ret <3 x i32> %t5
+}
+
+define <3 x i32> @t4_vec_nonsplat(<3 x i32> %x, <3 x i32> %nbits) {
+; CHECK-LABEL: @t4_vec_nonsplat(
+; CHECK-NEXT: [[T0:%.*]] = add <3 x i32> [[NBITS:%.*]], <i32 -1, i32 0, i32 1>
+; CHECK-NEXT: [[T1:%.*]] = shl <3 x i32> <i32 1, i32 1, i32 1>, [[T0]]
+; CHECK-NEXT: [[T2:%.*]] = add nsw <3 x i32> [[T1]], <i32 -1, i32 -1, i32 -1>
+; CHECK-NEXT: [[T3:%.*]] = and <3 x i32> [[T2]], [[X:%.*]]
+; CHECK-NEXT: [[T4:%.*]] = sub <3 x i32> <i32 33, i32 32, i32 32>, [[NBITS]]
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T0]])
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T1]])
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T2]])
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T3]])
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T4]])
+; CHECK-NEXT: [[T5:%.*]] = shl <3 x i32> [[T3]], [[T4]]
+; CHECK-NEXT: ret <3 x i32> [[T5]]
+;
+ %t0 = add <3 x i32> %nbits, <i32 -1, i32 0, i32 1>
+ %t1 = shl <3 x i32> <i32 1, i32 1, i32 1>, %t0
+ %t2 = add nsw <3 x i32> %t1, <i32 -1, i32 -1, i32 -1>
+ %t3 = and <3 x i32> %t2, %x
+ %t4 = sub <3 x i32> <i32 33, i32 32, i32 32>, %nbits
+ call void @use3xi32(<3 x i32> %t0)
+ call void @use3xi32(<3 x i32> %t1)
+ call void @use3xi32(<3 x i32> %t2)
+ call void @use3xi32(<3 x i32> %t3)
+ call void @use3xi32(<3 x i32> %t4)
+ %t5 = shl <3 x i32> %t3, %t4
+ ret <3 x i32> %t5
+}
+
+define <3 x i32> @t5_vec_undef(<3 x i32> %x, <3 x i32> %nbits) {
+; CHECK-LABEL: @t5_vec_undef(
+; CHECK-NEXT: [[T1:%.*]] = shl <3 x i32> <i32 1, i32 undef, i32 1>, [[NBITS:%.*]]
+; CHECK-NEXT: [[T2:%.*]] = add nsw <3 x i32> [[T1]], <i32 -1, i32 undef, i32 -1>
+; CHECK-NEXT: [[T3:%.*]] = and <3 x i32> [[T2]], [[X:%.*]]
+; CHECK-NEXT: [[T4:%.*]] = sub <3 x i32> <i32 32, i32 undef, i32 32>, [[NBITS]]
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[NBITS]])
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T1]])
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T2]])
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T3]])
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T4]])
+; CHECK-NEXT: [[T5:%.*]] = shl <3 x i32> [[T3]], [[T4]]
+; CHECK-NEXT: ret <3 x i32> [[T5]]
+;
+ %t0 = add <3 x i32> %nbits, <i32 0, i32 undef, i32 0>
+ %t1 = shl <3 x i32> <i32 1, i32 undef, i32 1>, %t0
+ %t2 = add nsw <3 x i32> %t1, <i32 -1, i32 undef, i32 -1>
+ %t3 = and <3 x i32> %t2, %x
+ %t4 = sub <3 x i32> <i32 32, i32 undef, i32 32>, %nbits
+ call void @use3xi32(<3 x i32> %t0)
+ call void @use3xi32(<3 x i32> %t1)
+ call void @use3xi32(<3 x i32> %t2)
+ call void @use3xi32(<3 x i32> %t3)
+ call void @use3xi32(<3 x i32> %t4)
+ %t5 = shl <3 x i32> %t3, %t4
+ ret <3 x i32> %t5
+}
+
+; Commutativity
+
+declare i32 @gen32()
+
+define i32 @t6_commutativity0(i32 %nbits) {
+; CHECK-LABEL: @t6_commutativity0(
+; CHECK-NEXT: [[X:%.*]] = call i32 @gen32()
+; CHECK-NEXT: [[T0:%.*]] = shl i32 1, [[NBITS:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = add nsw i32 [[T0]], -1
+; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], [[T1]]
+; CHECK-NEXT: [[T3:%.*]] = sub i32 32, [[NBITS]]
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: call void @use32(i32 [[T2]])
+; CHECK-NEXT: call void @use32(i32 [[T3]])
+; CHECK-NEXT: [[T4:%.*]] = shl i32 [[T2]], [[T3]]
+; CHECK-NEXT: ret i32 [[T4]]
+;
+ %x = call i32 @gen32()
+ %t0 = shl i32 1, %nbits
+ %t1 = add nsw i32 %t0, -1
+ %t2 = and i32 %x, %t1 ; swapped
+ %t3 = sub i32 32, %nbits
+ call void @use32(i32 %t0)
+ call void @use32(i32 %t1)
+ call void @use32(i32 %t2)
+ call void @use32(i32 %t3)
+ %t4 = shl i32 %t2, %t3
+ ret i32 %t4
+}
+
+define i32 @t6_commutativity1(i32 %nbits0, i32 %nbits1) {
+; CHECK-LABEL: @t6_commutativity1(
+; CHECK-NEXT: [[T0:%.*]] = shl i32 1, [[NBITS0:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = add nsw i32 [[T0]], -1
+; CHECK-NEXT: [[T2:%.*]] = shl i32 1, [[NBITS1:%.*]]
+; CHECK-NEXT: [[T3:%.*]] = add nsw i32 [[T2]], -1
+; CHECK-NEXT: [[T4:%.*]] = and i32 [[T3]], [[T1]]
+; CHECK-NEXT: [[T5:%.*]] = sub i32 32, [[NBITS0]]
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: call void @use32(i32 [[T2]])
+; CHECK-NEXT: call void @use32(i32 [[T3]])
+; CHECK-NEXT: call void @use32(i32 [[T4]])
+; CHECK-NEXT: call void @use32(i32 [[T5]])
+; CHECK-NEXT: ret i32 [[T4]]
+;
+ %t0 = shl i32 1, %nbits0
+ %t1 = add nsw i32 %t0, -1
+ %t2 = shl i32 1, %nbits1
+ %t3 = add nsw i32 %t2, -1
+ %t4 = and i32 %t3, %t1 ; both hands of 'and' could be mask..
+ %t5 = sub i32 32, %nbits0
+ call void @use32(i32 %t0)
+ call void @use32(i32 %t1)
+ call void @use32(i32 %t2)
+ call void @use32(i32 %t3)
+ call void @use32(i32 %t4)
+ call void @use32(i32 %t5)
+ %t6 = shl i32 %t4, %t5
+ ret i32 %t4
+}
+define i32 @t6_commutativity2(i32 %nbits0, i32 %nbits1) {
+; CHECK-LABEL: @t6_commutativity2(
+; CHECK-NEXT: [[T0:%.*]] = shl i32 1, [[NBITS0:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = add nsw i32 [[T0]], -1
+; CHECK-NEXT: [[T2:%.*]] = shl i32 1, [[NBITS1:%.*]]
+; CHECK-NEXT: [[T3:%.*]] = add nsw i32 [[T2]], -1
+; CHECK-NEXT: [[T4:%.*]] = and i32 [[T3]], [[T1]]
+; CHECK-NEXT: [[T5:%.*]] = sub i32 32, [[NBITS1]]
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: call void @use32(i32 [[T2]])
+; CHECK-NEXT: call void @use32(i32 [[T3]])
+; CHECK-NEXT: call void @use32(i32 [[T4]])
+; CHECK-NEXT: call void @use32(i32 [[T5]])
+; CHECK-NEXT: ret i32 [[T4]]
+;
+ %t0 = shl i32 1, %nbits0
+ %t1 = add nsw i32 %t0, -1
+ %t2 = shl i32 1, %nbits1
+ %t3 = add nsw i32 %t2, -1
+ %t4 = and i32 %t3, %t1 ; both hands of 'and' could be mask..
+ %t5 = sub i32 32, %nbits1
+ call void @use32(i32 %t0)
+ call void @use32(i32 %t1)
+ call void @use32(i32 %t2)
+ call void @use32(i32 %t3)
+ call void @use32(i32 %t4)
+ call void @use32(i32 %t5)
+ %t6 = shl i32 %t4, %t5
+ ret i32 %t4
+}
+
+; Fast-math flags. We must not preserve them!
+
+define i32 @t7_nuw(i32 %x, i32 %nbits) {
+; CHECK-LABEL: @t7_nuw(
+; CHECK-NEXT: [[T0:%.*]] = shl i32 1, [[NBITS:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = add nsw i32 [[T0]], -1
+; CHECK-NEXT: [[T2:%.*]] = and i32 [[T1]], [[X:%.*]]
+; CHECK-NEXT: [[T3:%.*]] = sub i32 32, [[NBITS]]
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: call void @use32(i32 [[T2]])
+; CHECK-NEXT: call void @use32(i32 [[T3]])
+; CHECK-NEXT: [[T4:%.*]] = shl nuw i32 [[T2]], [[T3]]
+; CHECK-NEXT: ret i32 [[T4]]
+;
+ %t0 = shl i32 1, %nbits
+ %t1 = add nsw i32 %t0, -1
+ %t2 = and i32 %t1, %x
+ %t3 = sub i32 32, %nbits
+ call void @use32(i32 %t0)
+ call void @use32(i32 %t1)
+ call void @use32(i32 %t2)
+ call void @use32(i32 %t3)
+ %t4 = shl nuw i32 %t2, %t3
+ ret i32 %t4
+}
+
+define i32 @t8_nsw(i32 %x, i32 %nbits) {
+; CHECK-LABEL: @t8_nsw(
+; CHECK-NEXT: [[T0:%.*]] = shl i32 1, [[NBITS:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = add nsw i32 [[T0]], -1
+; CHECK-NEXT: [[T2:%.*]] = and i32 [[T1]], [[X:%.*]]
+; CHECK-NEXT: [[T3:%.*]] = sub i32 32, [[NBITS]]
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: call void @use32(i32 [[T2]])
+; CHECK-NEXT: call void @use32(i32 [[T3]])
+; CHECK-NEXT: [[T4:%.*]] = shl nsw i32 [[T2]], [[T3]]
+; CHECK-NEXT: ret i32 [[T4]]
+;
+ %t0 = shl i32 1, %nbits
+ %t1 = add nsw i32 %t0, -1
+ %t2 = and i32 %t1, %x
+ %t3 = sub i32 32, %nbits
+ call void @use32(i32 %t0)
+ call void @use32(i32 %t1)
+ call void @use32(i32 %t2)
+ call void @use32(i32 %t3)
+ %t4 = shl nsw i32 %t2, %t3
+ ret i32 %t4
+}
+
+define i32 @t9_nuw_nsw(i32 %x, i32 %nbits) {
+; CHECK-LABEL: @t9_nuw_nsw(
+; CHECK-NEXT: [[T0:%.*]] = shl i32 1, [[NBITS:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = add nsw i32 [[T0]], -1
+; CHECK-NEXT: [[T2:%.*]] = and i32 [[T1]], [[X:%.*]]
+; CHECK-NEXT: [[T3:%.*]] = sub i32 32, [[NBITS]]
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: call void @use32(i32 [[T2]])
+; CHECK-NEXT: call void @use32(i32 [[T3]])
+; CHECK-NEXT: [[T4:%.*]] = shl nuw nsw i32 [[T2]], [[T3]]
+; CHECK-NEXT: ret i32 [[T4]]
+;
+ %t0 = shl i32 1, %nbits
+ %t1 = add nsw i32 %t0, -1
+ %t2 = and i32 %t1, %x
+ %t3 = sub i32 32, %nbits
+ call void @use32(i32 %t0)
+ call void @use32(i32 %t1)
+ call void @use32(i32 %t2)
+ call void @use32(i32 %t3)
+ %t4 = shl nuw nsw i32 %t2, %t3
+ ret i32 %t4
+}
+
+; Negative tests
+
+define i32 @n10(i32 %x, i32 %nbits) {
+; CHECK-LABEL: @n10(
+; CHECK-NEXT: [[T0:%.*]] = shl i32 2, [[NBITS:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = add nsw i32 [[T0]], -1
+; CHECK-NEXT: [[T2:%.*]] = and i32 [[T1]], [[X:%.*]]
+; CHECK-NEXT: [[T3:%.*]] = sub i32 32, [[NBITS]]
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: call void @use32(i32 [[T2]])
+; CHECK-NEXT: call void @use32(i32 [[T3]])
+; CHECK-NEXT: [[T4:%.*]] = shl i32 [[T2]], [[T3]]
+; CHECK-NEXT: ret i32 [[T4]]
+;
+ %t0 = shl i32 2, %nbits ; shifting not '-1'
+ %t1 = add nsw i32 %t0, -1
+ %t2 = and i32 %t1, %x
+ %t3 = sub i32 32, %nbits
+ call void @use32(i32 %t0)
+ call void @use32(i32 %t1)
+ call void @use32(i32 %t2)
+ call void @use32(i32 %t3)
+ %t4 = shl i32 %t2, %t3
+ ret i32 %t4
+}
+
+define i32 @n11(i32 %x, i32 %nbits) {
+; CHECK-LABEL: @n11(
+; CHECK-NEXT: [[T0:%.*]] = shl i32 1, [[NBITS:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = add nsw i32 [[T0]], 2147483647
+; CHECK-NEXT: [[T2:%.*]] = and i32 [[T1]], [[X:%.*]]
+; CHECK-NEXT: [[T3:%.*]] = sub i32 32, [[NBITS]]
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: call void @use32(i32 [[T2]])
+; CHECK-NEXT: call void @use32(i32 [[T3]])
+; CHECK-NEXT: [[T4:%.*]] = shl i32 [[T2]], [[T3]]
+; CHECK-NEXT: ret i32 [[T4]]
+;
+ %t0 = shl i32 1, %nbits
+ %t1 = add nsw i32 %t0, 2147483647 ; adding not '-1'
+ %t2 = and i32 %t1, %x
+ %t3 = sub i32 32, %nbits
+ call void @use32(i32 %t0)
+ call void @use32(i32 %t1)
+ call void @use32(i32 %t2)
+ call void @use32(i32 %t3)
+ %t4 = shl i32 %t2, %t3
+ ret i32 %t4
+}
+
+define i32 @n12(i32 %x, i32 %nbits) {
+; CHECK-LABEL: @n12(
+; CHECK-NEXT: [[T0:%.*]] = shl i32 1, [[NBITS:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = add nsw i32 [[T0]], -1
+; CHECK-NEXT: [[T2:%.*]] = and i32 [[T1]], [[X:%.*]]
+; CHECK-NEXT: [[T3:%.*]] = sub i32 31, [[NBITS]]
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: call void @use32(i32 [[T2]])
+; CHECK-NEXT: call void @use32(i32 [[T3]])
+; CHECK-NEXT: [[T4:%.*]] = shl i32 [[T2]], [[T3]]
+; CHECK-NEXT: ret i32 [[T4]]
+;
+ %t0 = shl i32 1, %nbits
+ %t1 = add nsw i32 %t0, -1
+ %t2 = and i32 %t1, %x
+ %t3 = sub i32 31, %nbits ; summary shift amount is less than 32
+ call void @use32(i32 %t0)
+ call void @use32(i32 %t1)
+ call void @use32(i32 %t2)
+ call void @use32(i32 %t3)
+ %t4 = shl i32 %t2, %t3
+ ret i32 %t4
+}
Added: llvm/trunk/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-b.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-b.ll?rev=365641&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-b.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-b.ll Wed Jul 10 08:08:06 2019
@@ -0,0 +1,407 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt %s -instcombine -S | FileCheck %s
+
+; If we have some pattern that leaves only some low bits set, and then performs
+; left-shift of those bits, if none of the bits that are left after the final
+; shift are modified by the mask, we can omit the mask.
+
+; There are many variants to this pattern:
+; b) (x & (~(-1 << maskNbits))) << shiftNbits
+; simplify to:
+; x << shiftNbits
+; iff (maskNbits+shiftNbits) u>= bitwidth(x)
+
+; Simple tests. We don't care about extra uses.
+
+declare void @use32(i32)
+
+define i32 @t0_basic(i32 %x, i32 %nbits) {
+; CHECK-LABEL: @t0_basic(
+; CHECK-NEXT: [[T0:%.*]] = shl i32 -1, [[NBITS:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = xor i32 [[T0]], -1
+; CHECK-NEXT: [[T2:%.*]] = and i32 [[T1]], [[X:%.*]]
+; CHECK-NEXT: [[T3:%.*]] = sub i32 32, [[NBITS]]
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: call void @use32(i32 [[T2]])
+; CHECK-NEXT: call void @use32(i32 [[T3]])
+; CHECK-NEXT: [[T4:%.*]] = shl i32 [[T2]], [[T3]]
+; CHECK-NEXT: ret i32 [[T4]]
+;
+ %t0 = shl i32 -1, %nbits
+ %t1 = xor i32 %t0, -1
+ %t2 = and i32 %t1, %x
+ %t3 = sub i32 32, %nbits
+ call void @use32(i32 %t0)
+ call void @use32(i32 %t1)
+ call void @use32(i32 %t2)
+ call void @use32(i32 %t3)
+ %t4 = shl i32 %t2, %t3
+ ret i32 %t4
+}
+
+define i32 @t1_bigger_shift(i32 %x, i32 %nbits) {
+; CHECK-LABEL: @t1_bigger_shift(
+; CHECK-NEXT: [[T0:%.*]] = shl i32 -1, [[NBITS:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = xor i32 [[T0]], -1
+; CHECK-NEXT: [[T2:%.*]] = and i32 [[T1]], [[X:%.*]]
+; CHECK-NEXT: [[T3:%.*]] = sub i32 33, [[NBITS]]
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: call void @use32(i32 [[T2]])
+; CHECK-NEXT: call void @use32(i32 [[T3]])
+; CHECK-NEXT: [[T4:%.*]] = shl i32 [[T2]], [[T3]]
+; CHECK-NEXT: ret i32 [[T4]]
+;
+ %t0 = shl i32 -1, %nbits
+ %t1 = xor i32 %t0, -1
+ %t2 = and i32 %t1, %x
+ %t3 = sub i32 33, %nbits ; subtracting from bitwidth+1
+ call void @use32(i32 %t0)
+ call void @use32(i32 %t1)
+ call void @use32(i32 %t2)
+ call void @use32(i32 %t3)
+ %t4 = shl i32 %t2, %t3
+ ret i32 %t4
+}
+
+define i32 @t2_bigger_mask(i32 %x, i32 %nbits) {
+; CHECK-LABEL: @t2_bigger_mask(
+; CHECK-NEXT: [[T0:%.*]] = add i32 [[NBITS:%.*]], 1
+; CHECK-NEXT: [[T1:%.*]] = shl i32 -1, [[T0]]
+; CHECK-NEXT: [[T2:%.*]] = xor i32 [[T1]], -1
+; CHECK-NEXT: [[T3:%.*]] = and i32 [[T2]], [[X:%.*]]
+; CHECK-NEXT: [[T4:%.*]] = sub i32 32, [[NBITS]]
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: call void @use32(i32 [[T2]])
+; CHECK-NEXT: call void @use32(i32 [[T3]])
+; CHECK-NEXT: call void @use32(i32 [[T4]])
+; CHECK-NEXT: [[T5:%.*]] = shl i32 [[T3]], [[T4]]
+; CHECK-NEXT: ret i32 [[T5]]
+;
+ %t0 = add i32 %nbits, 1
+ %t1 = shl i32 -1, %t0 ; shifting by nbits+1
+ %t2 = xor i32 %t1, -1
+ %t3 = and i32 %t2, %x
+ %t4 = sub i32 32, %nbits
+ call void @use32(i32 %t0)
+ call void @use32(i32 %t1)
+ call void @use32(i32 %t2)
+ call void @use32(i32 %t3)
+ call void @use32(i32 %t4)
+ %t5 = shl i32 %t3, %t4
+ ret i32 %t5
+}
+
+; Vectors
+
+declare void @use3xi32(<3 x i32>)
+
+define <3 x i32> @t3_vec_splat(<3 x i32> %x, <3 x i32> %nbits) {
+; CHECK-LABEL: @t3_vec_splat(
+; CHECK-NEXT: [[T1:%.*]] = shl <3 x i32> <i32 -1, i32 -1, i32 -1>, [[NBITS:%.*]]
+; CHECK-NEXT: [[T2:%.*]] = xor <3 x i32> [[T1]], <i32 -1, i32 -1, i32 -1>
+; CHECK-NEXT: [[T3:%.*]] = and <3 x i32> [[T2]], [[X:%.*]]
+; CHECK-NEXT: [[T4:%.*]] = sub <3 x i32> <i32 32, i32 32, i32 32>, [[NBITS]]
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[NBITS]])
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T1]])
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T2]])
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T3]])
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T4]])
+; CHECK-NEXT: [[T5:%.*]] = shl <3 x i32> [[T3]], [[T4]]
+; CHECK-NEXT: ret <3 x i32> [[T5]]
+;
+ %t0 = add <3 x i32> %nbits, <i32 0, i32 0, i32 0>
+ %t1 = shl <3 x i32> <i32 -1, i32 -1, i32 -1>, %t0
+ %t2 = xor <3 x i32> %t1, <i32 -1, i32 -1, i32 -1>
+ %t3 = and <3 x i32> %t2, %x
+ %t4 = sub <3 x i32> <i32 32, i32 32, i32 32>, %nbits
+ call void @use3xi32(<3 x i32> %t0)
+ call void @use3xi32(<3 x i32> %t1)
+ call void @use3xi32(<3 x i32> %t2)
+ call void @use3xi32(<3 x i32> %t3)
+ call void @use3xi32(<3 x i32> %t4)
+ %t5 = shl <3 x i32> %t3, %t4
+ ret <3 x i32> %t5
+}
+
+define <3 x i32> @t4_vec_nonsplat(<3 x i32> %x, <3 x i32> %nbits) {
+; CHECK-LABEL: @t4_vec_nonsplat(
+; CHECK-NEXT: [[T0:%.*]] = add <3 x i32> [[NBITS:%.*]], <i32 -1, i32 0, i32 1>
+; CHECK-NEXT: [[T1:%.*]] = shl <3 x i32> <i32 -1, i32 -1, i32 -1>, [[T0]]
+; CHECK-NEXT: [[T2:%.*]] = xor <3 x i32> [[T1]], <i32 -1, i32 -1, i32 -1>
+; CHECK-NEXT: [[T3:%.*]] = and <3 x i32> [[T2]], [[X:%.*]]
+; CHECK-NEXT: [[T4:%.*]] = sub <3 x i32> <i32 33, i32 32, i32 32>, [[NBITS]]
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T0]])
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T1]])
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T2]])
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T3]])
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T4]])
+; CHECK-NEXT: [[T5:%.*]] = shl <3 x i32> [[T3]], [[T4]]
+; CHECK-NEXT: ret <3 x i32> [[T5]]
+;
+ %t0 = add <3 x i32> %nbits, <i32 -1, i32 0, i32 1>
+ %t1 = shl <3 x i32> <i32 -1, i32 -1, i32 -1>, %t0
+ %t2 = xor <3 x i32> %t1, <i32 -1, i32 -1, i32 -1>
+ %t3 = and <3 x i32> %t2, %x
+ %t4 = sub <3 x i32> <i32 33, i32 32, i32 32>, %nbits
+ call void @use3xi32(<3 x i32> %t0)
+ call void @use3xi32(<3 x i32> %t1)
+ call void @use3xi32(<3 x i32> %t2)
+ call void @use3xi32(<3 x i32> %t3)
+ call void @use3xi32(<3 x i32> %t4)
+ %t5 = shl <3 x i32> %t3, %t4
+ ret <3 x i32> %t5
+}
+
+define <3 x i32> @t5_vec_undef(<3 x i32> %x, <3 x i32> %nbits) {
+; CHECK-LABEL: @t5_vec_undef(
+; CHECK-NEXT: [[T1:%.*]] = shl <3 x i32> <i32 -1, i32 undef, i32 -1>, [[NBITS:%.*]]
+; CHECK-NEXT: [[T2:%.*]] = xor <3 x i32> [[T1]], <i32 -1, i32 undef, i32 -1>
+; CHECK-NEXT: [[T3:%.*]] = and <3 x i32> [[T2]], [[X:%.*]]
+; CHECK-NEXT: [[T4:%.*]] = sub <3 x i32> <i32 32, i32 undef, i32 32>, [[NBITS]]
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[NBITS]])
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T1]])
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T2]])
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T3]])
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T4]])
+; CHECK-NEXT: [[T5:%.*]] = shl <3 x i32> [[T3]], [[T4]]
+; CHECK-NEXT: ret <3 x i32> [[T5]]
+;
+ %t0 = add <3 x i32> %nbits, <i32 0, i32 undef, i32 0>
+ %t1 = shl <3 x i32> <i32 -1, i32 undef, i32 -1>, %t0
+ %t2 = xor <3 x i32> %t1, <i32 -1, i32 undef, i32 -1>
+ %t3 = and <3 x i32> %t2, %x
+ %t4 = sub <3 x i32> <i32 32, i32 undef, i32 32>, %nbits
+ call void @use3xi32(<3 x i32> %t0)
+ call void @use3xi32(<3 x i32> %t1)
+ call void @use3xi32(<3 x i32> %t2)
+ call void @use3xi32(<3 x i32> %t3)
+ call void @use3xi32(<3 x i32> %t4)
+ %t5 = shl <3 x i32> %t3, %t4
+ ret <3 x i32> %t5
+}
+
+; Commutativity
+
+declare i32 @gen32()
+
+define i32 @t6_commutativity0(i32 %nbits) {
+; CHECK-LABEL: @t6_commutativity0(
+; CHECK-NEXT: [[X:%.*]] = call i32 @gen32()
+; CHECK-NEXT: [[T0:%.*]] = shl i32 -1, [[NBITS:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = xor i32 [[T0]], -1
+; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], [[T1]]
+; CHECK-NEXT: [[T3:%.*]] = sub i32 32, [[NBITS]]
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: call void @use32(i32 [[T2]])
+; CHECK-NEXT: call void @use32(i32 [[T3]])
+; CHECK-NEXT: [[T4:%.*]] = shl i32 [[T2]], [[T3]]
+; CHECK-NEXT: ret i32 [[T4]]
+;
+ %x = call i32 @gen32()
+ %t0 = shl i32 -1, %nbits
+ %t1 = xor i32 %t0, -1
+ %t2 = and i32 %x, %t1 ; swapped
+ %t3 = sub i32 32, %nbits
+ call void @use32(i32 %t0)
+ call void @use32(i32 %t1)
+ call void @use32(i32 %t2)
+ call void @use32(i32 %t3)
+ %t4 = shl i32 %t2, %t3
+ ret i32 %t4
+}
+
+define i32 @t6_commutativity1(i32 %nbits0, i32 %nbits1) {
+; CHECK-LABEL: @t6_commutativity1(
+; CHECK-NEXT: [[T0:%.*]] = shl i32 -1, [[NBITS0:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = xor i32 [[T0]], -1
+; CHECK-NEXT: [[T2:%.*]] = shl i32 -1, [[NBITS1:%.*]]
+; CHECK-NEXT: [[T3:%.*]] = xor i32 [[T2]], -1
+; CHECK-NEXT: [[T4:%.*]] = and i32 [[T3]], [[T1]]
+; CHECK-NEXT: [[T5:%.*]] = sub i32 32, [[NBITS0]]
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: call void @use32(i32 [[T2]])
+; CHECK-NEXT: call void @use32(i32 [[T3]])
+; CHECK-NEXT: call void @use32(i32 [[T4]])
+; CHECK-NEXT: call void @use32(i32 [[T5]])
+; CHECK-NEXT: ret i32 [[T4]]
+;
+ %t0 = shl i32 -1, %nbits0
+ %t1 = xor i32 %t0, -1
+ %t2 = shl i32 -1, %nbits1
+ %t3 = xor i32 %t2, -1
+ %t4 = and i32 %t3, %t1 ; both hands of 'and' could be mask..
+ %t5 = sub i32 32, %nbits0
+ call void @use32(i32 %t0)
+ call void @use32(i32 %t1)
+ call void @use32(i32 %t2)
+ call void @use32(i32 %t3)
+ call void @use32(i32 %t4)
+ call void @use32(i32 %t5)
+ %t6 = shl i32 %t4, %t5
+ ret i32 %t4
+}
+define i32 @t6_commutativity2(i32 %nbits0, i32 %nbits1) {
+; CHECK-LABEL: @t6_commutativity2(
+; CHECK-NEXT: [[T0:%.*]] = shl i32 -1, [[NBITS0:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = xor i32 [[T0]], -1
+; CHECK-NEXT: [[T2:%.*]] = shl i32 -1, [[NBITS1:%.*]]
+; CHECK-NEXT: [[T3:%.*]] = xor i32 [[T2]], -1
+; CHECK-NEXT: [[T4:%.*]] = and i32 [[T3]], [[T1]]
+; CHECK-NEXT: [[T5:%.*]] = sub i32 32, [[NBITS1]]
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: call void @use32(i32 [[T2]])
+; CHECK-NEXT: call void @use32(i32 [[T3]])
+; CHECK-NEXT: call void @use32(i32 [[T4]])
+; CHECK-NEXT: call void @use32(i32 [[T5]])
+; CHECK-NEXT: ret i32 [[T4]]
+;
+ %t0 = shl i32 -1, %nbits0
+ %t1 = xor i32 %t0, -1
+ %t2 = shl i32 -1, %nbits1
+ %t3 = xor i32 %t2, -1
+ %t4 = and i32 %t3, %t1 ; both hands of 'and' could be mask..
+ %t5 = sub i32 32, %nbits1
+ call void @use32(i32 %t0)
+ call void @use32(i32 %t1)
+ call void @use32(i32 %t2)
+ call void @use32(i32 %t3)
+ call void @use32(i32 %t4)
+ call void @use32(i32 %t5)
+ %t6 = shl i32 %t4, %t5
+ ret i32 %t4
+}
+
+; Fast-math flags. We must not preserve them!
+
+define i32 @t7_nuw(i32 %x, i32 %nbits) {
+; CHECK-LABEL: @t7_nuw(
+; CHECK-NEXT: [[T0:%.*]] = shl i32 -1, [[NBITS:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = xor i32 [[T0]], -1
+; CHECK-NEXT: [[T2:%.*]] = and i32 [[T1]], [[X:%.*]]
+; CHECK-NEXT: [[T3:%.*]] = sub i32 32, [[NBITS]]
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: call void @use32(i32 [[T2]])
+; CHECK-NEXT: call void @use32(i32 [[T3]])
+; CHECK-NEXT: [[T4:%.*]] = shl nuw i32 [[T2]], [[T3]]
+; CHECK-NEXT: ret i32 [[T4]]
+;
+ %t0 = shl i32 -1, %nbits
+ %t1 = xor i32 %t0, -1
+ %t2 = and i32 %t1, %x
+ %t3 = sub i32 32, %nbits
+ call void @use32(i32 %t0)
+ call void @use32(i32 %t1)
+ call void @use32(i32 %t2)
+ call void @use32(i32 %t3)
+ %t4 = shl nuw i32 %t2, %t3
+ ret i32 %t4
+}
+
+define i32 @t8_nsw(i32 %x, i32 %nbits) {
+; CHECK-LABEL: @t8_nsw(
+; CHECK-NEXT: [[T0:%.*]] = shl i32 -1, [[NBITS:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = xor i32 [[T0]], -1
+; CHECK-NEXT: [[T2:%.*]] = and i32 [[T1]], [[X:%.*]]
+; CHECK-NEXT: [[T3:%.*]] = sub i32 32, [[NBITS]]
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: call void @use32(i32 [[T2]])
+; CHECK-NEXT: call void @use32(i32 [[T3]])
+; CHECK-NEXT: [[T4:%.*]] = shl nsw i32 [[T2]], [[T3]]
+; CHECK-NEXT: ret i32 [[T4]]
+;
+ %t0 = shl i32 -1, %nbits
+ %t1 = xor i32 %t0, -1
+ %t2 = and i32 %t1, %x
+ %t3 = sub i32 32, %nbits
+ call void @use32(i32 %t0)
+ call void @use32(i32 %t1)
+ call void @use32(i32 %t2)
+ call void @use32(i32 %t3)
+ %t4 = shl nsw i32 %t2, %t3
+ ret i32 %t4
+}
+
+define i32 @t9_nuw_nsw(i32 %x, i32 %nbits) {
+; CHECK-LABEL: @t9_nuw_nsw(
+; CHECK-NEXT: [[T0:%.*]] = shl i32 -1, [[NBITS:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = xor i32 [[T0]], -1
+; CHECK-NEXT: [[T2:%.*]] = and i32 [[T1]], [[X:%.*]]
+; CHECK-NEXT: [[T3:%.*]] = sub i32 32, [[NBITS]]
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: call void @use32(i32 [[T2]])
+; CHECK-NEXT: call void @use32(i32 [[T3]])
+; CHECK-NEXT: [[T4:%.*]] = shl nuw nsw i32 [[T2]], [[T3]]
+; CHECK-NEXT: ret i32 [[T4]]
+;
+ %t0 = shl i32 -1, %nbits
+ %t1 = xor i32 %t0, -1
+ %t2 = and i32 %t1, %x
+ %t3 = sub i32 32, %nbits
+ call void @use32(i32 %t0)
+ call void @use32(i32 %t1)
+ call void @use32(i32 %t2)
+ call void @use32(i32 %t3)
+ %t4 = shl nuw nsw i32 %t2, %t3
+ ret i32 %t4
+}
+
+; Negative tests
+
+define i32 @n10(i32 %x, i32 %nbits) {
+; CHECK-LABEL: @n10(
+; CHECK-NEXT: [[T0:%.*]] = shl i32 -2, [[NBITS:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = xor i32 [[T0]], -1
+; CHECK-NEXT: [[T2:%.*]] = and i32 [[T1]], [[X:%.*]]
+; CHECK-NEXT: [[T3:%.*]] = sub i32 32, [[NBITS]]
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: call void @use32(i32 [[T2]])
+; CHECK-NEXT: call void @use32(i32 [[T3]])
+; CHECK-NEXT: [[T4:%.*]] = shl i32 [[T2]], [[T3]]
+; CHECK-NEXT: ret i32 [[T4]]
+;
+ %t0 = shl i32 -2, %nbits ; shifting not '-1'
+ %t1 = xor i32 %t0, -1
+ %t2 = and i32 %t1, %x
+ %t3 = sub i32 32, %nbits
+ call void @use32(i32 %t0)
+ call void @use32(i32 %t1)
+ call void @use32(i32 %t2)
+ call void @use32(i32 %t3)
+ %t4 = shl i32 %t2, %t3
+ ret i32 %t4
+}
+
+define i32 @n11(i32 %x, i32 %nbits) {
+; CHECK-LABEL: @n11(
+; CHECK-NEXT: [[T0:%.*]] = shl i32 -1, [[NBITS:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = xor i32 [[T0]], -1
+; CHECK-NEXT: [[T2:%.*]] = and i32 [[T1]], [[X:%.*]]
+; CHECK-NEXT: [[T3:%.*]] = sub i32 31, [[NBITS]]
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: call void @use32(i32 [[T2]])
+; CHECK-NEXT: call void @use32(i32 [[T3]])
+; CHECK-NEXT: [[T4:%.*]] = shl i32 [[T2]], [[T3]]
+; CHECK-NEXT: ret i32 [[T4]]
+;
+ %t0 = shl i32 -1, %nbits
+ %t1 = xor i32 %t0, -1
+ %t2 = and i32 %t1, %x
+ %t3 = sub i32 31, %nbits ; summary shift amount is less than 32
+ call void @use32(i32 %t0)
+ call void @use32(i32 %t1)
+ call void @use32(i32 %t2)
+ call void @use32(i32 %t3)
+ %t4 = shl i32 %t2, %t3
+ ret i32 %t4
+}
Added: llvm/trunk/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-c.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-c.ll?rev=365641&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-c.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-c.ll Wed Jul 10 08:08:06 2019
@@ -0,0 +1,277 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt %s -instcombine -S | FileCheck %s
+
+; If we have some pattern that leaves only some low bits set, and then performs
+; left-shift of those bits, if none of the bits that are left after the final
+; shift are modified by the mask, we can omit the mask.
+
+; There are many variants to this pattern:
+; c) (x & (-1 >> maskNbits)) << shiftNbits
+; simplify to:
+; x << shiftNbits
+; iff (shiftNbits-maskNbits) s>= 0 (i.e. shiftNbits u>= maskNbits)
+
+; Simple tests. We don't care about extra uses.
+
+declare void @use32(i32)
+
+define i32 @t0_basic(i32 %x, i32 %nbits) {
+; CHECK-LABEL: @t0_basic(
+; CHECK-NEXT: [[T0:%.*]] = lshr i32 -1, [[NBITS:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[X:%.*]]
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: [[T2:%.*]] = shl i32 [[T1]], [[NBITS]]
+; CHECK-NEXT: ret i32 [[T2]]
+;
+ %t0 = lshr i32 -1, %nbits
+ %t1 = and i32 %t0, %x
+ call void @use32(i32 %t0)
+ call void @use32(i32 %t1)
+ %t2 = shl i32 %t1, %nbits
+ ret i32 %t2
+}
+
+define i32 @t1_bigger_shift(i32 %x, i32 %nbits) {
+; CHECK-LABEL: @t1_bigger_shift(
+; CHECK-NEXT: [[T0:%.*]] = lshr i32 -1, [[NBITS:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[X:%.*]]
+; CHECK-NEXT: [[T2:%.*]] = add i32 [[NBITS]], 1
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: call void @use32(i32 [[T2]])
+; CHECK-NEXT: [[T3:%.*]] = shl i32 [[T1]], [[T2]]
+; CHECK-NEXT: ret i32 [[T3]]
+;
+ %t0 = lshr i32 -1, %nbits
+ %t1 = and i32 %t0, %x
+ %t2 = add i32 %nbits, 1
+ call void @use32(i32 %t0)
+ call void @use32(i32 %t1)
+ call void @use32(i32 %t2)
+ %t3 = shl i32 %t1, %t2
+ ret i32 %t3
+}
+
+; Vectors
+
+declare void @use3xi32(<3 x i32>)
+
+define <3 x i32> @t2_vec_splat(<3 x i32> %x, <3 x i32> %nbits) {
+; CHECK-LABEL: @t2_vec_splat(
+; CHECK-NEXT: [[T0:%.*]] = lshr <3 x i32> <i32 -1, i32 -1, i32 -1>, [[NBITS:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = and <3 x i32> [[T0]], [[X:%.*]]
+; CHECK-NEXT: [[T2:%.*]] = add <3 x i32> [[NBITS]], <i32 1, i32 1, i32 1>
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T0]])
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T1]])
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T2]])
+; CHECK-NEXT: [[T3:%.*]] = shl <3 x i32> [[T1]], [[T2]]
+; CHECK-NEXT: ret <3 x i32> [[T3]]
+;
+ %t0 = lshr <3 x i32> <i32 -1, i32 -1, i32 -1>, %nbits
+ %t1 = and <3 x i32> %t0, %x
+ %t2 = add <3 x i32> %nbits, <i32 1, i32 1, i32 1>
+ call void @use3xi32(<3 x i32> %t0)
+ call void @use3xi32(<3 x i32> %t1)
+ call void @use3xi32(<3 x i32> %t2)
+ %t3 = shl <3 x i32> %t1, %t2
+ ret <3 x i32> %t3
+}
+
+define <3 x i32> @t3_vec_nonsplat(<3 x i32> %x, <3 x i32> %nbits) {
+; CHECK-LABEL: @t3_vec_nonsplat(
+; CHECK-NEXT: [[T0:%.*]] = lshr <3 x i32> <i32 -1, i32 -1, i32 -1>, [[NBITS:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = and <3 x i32> [[T0]], [[X:%.*]]
+; CHECK-NEXT: [[T2:%.*]] = add <3 x i32> [[NBITS]], <i32 1, i32 0, i32 2>
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T0]])
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T1]])
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T2]])
+; CHECK-NEXT: [[T3:%.*]] = shl <3 x i32> [[T1]], [[T2]]
+; CHECK-NEXT: ret <3 x i32> [[T3]]
+;
+ %t0 = lshr <3 x i32> <i32 -1, i32 -1, i32 -1>, %nbits
+ %t1 = and <3 x i32> %t0, %x
+ %t2 = add <3 x i32> %nbits, <i32 1, i32 0, i32 2>
+ call void @use3xi32(<3 x i32> %t0)
+ call void @use3xi32(<3 x i32> %t1)
+ call void @use3xi32(<3 x i32> %t2)
+ %t3 = shl <3 x i32> %t1, %t2
+ ret <3 x i32> %t3
+}
+
+define <3 x i32> @t4_vec_undef(<3 x i32> %x, <3 x i32> %nbits) {
+; CHECK-LABEL: @t4_vec_undef(
+; CHECK-NEXT: [[T0:%.*]] = lshr <3 x i32> <i32 -1, i32 undef, i32 -1>, [[NBITS:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = and <3 x i32> [[T0]], [[X:%.*]]
+; CHECK-NEXT: [[T2:%.*]] = add <3 x i32> [[NBITS]], <i32 1, i32 undef, i32 1>
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T0]])
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T1]])
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T2]])
+; CHECK-NEXT: [[T3:%.*]] = shl <3 x i32> [[T1]], [[T2]]
+; CHECK-NEXT: ret <3 x i32> [[T3]]
+;
+ %t0 = lshr <3 x i32> <i32 -1, i32 undef, i32 -1>, %nbits
+ %t1 = and <3 x i32> %t0, %x
+ %t2 = add <3 x i32> %nbits, <i32 1, i32 undef, i32 1>
+ call void @use3xi32(<3 x i32> %t0)
+ call void @use3xi32(<3 x i32> %t1)
+ call void @use3xi32(<3 x i32> %t2)
+ %t3 = shl <3 x i32> %t1, %t2
+ ret <3 x i32> %t3
+}
+
+; Commutativity
+
+declare i32 @gen32()
+
+define i32 @t5_commutativity0(i32 %nbits) {
+; CHECK-LABEL: @t5_commutativity0(
+; CHECK-NEXT: [[X:%.*]] = call i32 @gen32()
+; CHECK-NEXT: [[T0:%.*]] = lshr i32 -1, [[NBITS:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = and i32 [[X]], [[T0]]
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: [[T2:%.*]] = shl i32 [[T1]], [[NBITS]]
+; CHECK-NEXT: ret i32 [[T2]]
+;
+ %x = call i32 @gen32()
+ %t0 = lshr i32 -1, %nbits
+ %t1 = and i32 %x, %t0 ; swapped
+ call void @use32(i32 %t0)
+ call void @use32(i32 %t1)
+ %t2 = shl i32 %t1, %nbits
+ ret i32 %t2
+}
+
+define i32 @t6_commutativity1(i32 %nbits0, i32 %nbits1) {
+; CHECK-LABEL: @t6_commutativity1(
+; CHECK-NEXT: [[T0:%.*]] = lshr i32 -1, [[NBITS0:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = lshr i32 -1, [[NBITS1:%.*]]
+; CHECK-NEXT: [[T2:%.*]] = and i32 [[T0]], [[T1]]
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: call void @use32(i32 [[T2]])
+; CHECK-NEXT: [[T3:%.*]] = shl i32 [[T2]], [[NBITS0]]
+; CHECK-NEXT: ret i32 [[T3]]
+;
+ %t0 = lshr i32 -1, %nbits0
+ %t1 = lshr i32 -1, %nbits1
+ %t2 = and i32 %t0, %t1 ; both hands of 'and' could be mask..
+ call void @use32(i32 %t0)
+ call void @use32(i32 %t1)
+ call void @use32(i32 %t2)
+ %t3 = shl i32 %t2, %nbits0
+ ret i32 %t3
+}
+define i32 @t7_commutativity2(i32 %nbits0, i32 %nbits1) {
+; CHECK-LABEL: @t7_commutativity2(
+; CHECK-NEXT: [[T0:%.*]] = lshr i32 -1, [[NBITS0:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = lshr i32 -1, [[NBITS1:%.*]]
+; CHECK-NEXT: [[T2:%.*]] = and i32 [[T0]], [[T1]]
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: call void @use32(i32 [[T2]])
+; CHECK-NEXT: [[T3:%.*]] = shl i32 [[T2]], [[NBITS1]]
+; CHECK-NEXT: ret i32 [[T3]]
+;
+ %t0 = lshr i32 -1, %nbits0
+ %t1 = lshr i32 -1, %nbits1
+ %t2 = and i32 %t0, %t1 ; both hands of 'and' could be mask..
+ call void @use32(i32 %t0)
+ call void @use32(i32 %t1)
+ call void @use32(i32 %t2)
+ %t3 = shl i32 %t2, %nbits1
+ ret i32 %t3
+}
+
+; Fast-math flags. We must not preserve them!
+
+define i32 @t8_nuw(i32 %x, i32 %nbits) {
+; CHECK-LABEL: @t8_nuw(
+; CHECK-NEXT: [[T0:%.*]] = lshr i32 -1, [[NBITS:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[X:%.*]]
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: [[T2:%.*]] = shl nuw i32 [[T1]], [[NBITS]]
+; CHECK-NEXT: ret i32 [[T2]]
+;
+ %t0 = lshr i32 -1, %nbits
+ %t1 = and i32 %t0, %x
+ call void @use32(i32 %t0)
+ call void @use32(i32 %t1)
+ %t2 = shl nuw i32 %t1, %nbits
+ ret i32 %t2
+}
+
+define i32 @t9_nsw(i32 %x, i32 %nbits) {
+; CHECK-LABEL: @t9_nsw(
+; CHECK-NEXT: [[T0:%.*]] = lshr i32 -1, [[NBITS:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[X:%.*]]
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: [[T2:%.*]] = shl nsw i32 [[T1]], [[NBITS]]
+; CHECK-NEXT: ret i32 [[T2]]
+;
+ %t0 = lshr i32 -1, %nbits
+ %t1 = and i32 %t0, %x
+ call void @use32(i32 %t0)
+ call void @use32(i32 %t1)
+ %t2 = shl nsw i32 %t1, %nbits
+ ret i32 %t2
+}
+
+define i32 @t10_nuw_nsw(i32 %x, i32 %nbits) {
+; CHECK-LABEL: @t10_nuw_nsw(
+; CHECK-NEXT: [[T0:%.*]] = lshr i32 -1, [[NBITS:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[X:%.*]]
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: [[T2:%.*]] = shl nuw nsw i32 [[T1]], [[NBITS]]
+; CHECK-NEXT: ret i32 [[T2]]
+;
+ %t0 = lshr i32 -1, %nbits
+ %t1 = and i32 %t0, %x
+ call void @use32(i32 %t0)
+ call void @use32(i32 %t1)
+ %t2 = shl nuw nsw i32 %t1, %nbits
+ ret i32 %t2
+}
+
+; Negative tests
+
+define i32 @n11(i32 %x, i32 %nbits) {
+; CHECK-LABEL: @n11(
+; CHECK-NEXT: [[T0:%.*]] = lshr i32 -2, [[NBITS:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[X:%.*]]
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: [[T2:%.*]] = shl i32 [[T1]], [[NBITS]]
+; CHECK-NEXT: ret i32 [[T2]]
+;
+ %t0 = lshr i32 -2, %nbits ; shifting not '-1'
+ %t1 = and i32 %t0, %x
+ call void @use32(i32 %t0)
+ call void @use32(i32 %t1)
+ %t2 = shl i32 %t1, %nbits
+ ret i32 %t2
+}
+
+define i32 @n12(i32 %x, i32 %nbits) {
+; CHECK-LABEL: @n12(
+; CHECK-NEXT: [[T0:%.*]] = lshr i32 -1, [[NBITS:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[X:%.*]]
+; CHECK-NEXT: [[T2:%.*]] = add i32 [[NBITS]], -1
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: call void @use32(i32 [[T2]])
+; CHECK-NEXT: ret i32 [[T2]]
+;
+ %t0 = lshr i32 -1, %nbits
+ %t1 = and i32 %t0, %x
+ %t2 = add i32 %nbits, -1
+ call void @use32(i32 %t0)
+ call void @use32(i32 %t1)
+ call void @use32(i32 %t2)
+ %t3 = shl i32 %t1, %t2 ; shift is smaller than mask
+ ret i32 %t2
+}
Added: llvm/trunk/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-d.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-d.ll?rev=365641&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-d.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-d.ll Wed Jul 10 08:08:06 2019
@@ -0,0 +1,334 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt %s -instcombine -S | FileCheck %s
+
+; If we have some pattern that leaves only some low bits set, and then performs
+; left-shift of those bits, if none of the bits that are left after the final
+; shift are modified by the mask, we can omit the mask.
+
+; There are many variants to this pattern:
+; d) (x & ((-1 << maskNbits) >> maskNbits)) << shiftNbits
+; simplify to:
+; x << shiftNbits
+; iff (shiftNbits-maskNbits) s>= 0 (i.e. shiftNbits u>= maskNbits)
+
+; Simple tests. We don't care about extra uses.
+
+declare void @use32(i32)
+
+define i32 @t0_basic(i32 %x, i32 %nbits) {
+; CHECK-LABEL: @t0_basic(
+; CHECK-NEXT: [[T0:%.*]] = shl i32 -1, [[NBITS:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = lshr i32 [[T0]], [[NBITS]]
+; CHECK-NEXT: [[T2:%.*]] = and i32 [[T1]], [[X:%.*]]
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: call void @use32(i32 [[T2]])
+; CHECK-NEXT: [[T4:%.*]] = shl i32 [[T2]], [[NBITS]]
+; CHECK-NEXT: ret i32 [[T4]]
+;
+ %t0 = shl i32 -1, %nbits
+ %t1 = lshr i32 %t0, %nbits
+ %t2 = and i32 %t1, %x
+ call void @use32(i32 %t0)
+ call void @use32(i32 %t1)
+ call void @use32(i32 %t2)
+ %t4 = shl i32 %t2, %nbits
+ ret i32 %t4
+}
+
+define i32 @t1_bigger_shift(i32 %x, i32 %nbits) {
+; CHECK-LABEL: @t1_bigger_shift(
+; CHECK-NEXT: [[T0:%.*]] = shl i32 -1, [[NBITS:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = lshr i32 [[T0]], [[NBITS]]
+; CHECK-NEXT: [[T2:%.*]] = and i32 [[T1]], [[X:%.*]]
+; CHECK-NEXT: [[T3:%.*]] = add i32 [[NBITS]], 1
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: call void @use32(i32 [[T2]])
+; CHECK-NEXT: call void @use32(i32 [[T3]])
+; CHECK-NEXT: [[T4:%.*]] = shl i32 [[T2]], [[T3]]
+; CHECK-NEXT: ret i32 [[T4]]
+;
+ %t0 = shl i32 -1, %nbits
+ %t1 = lshr i32 %t0, %nbits
+ %t2 = and i32 %t1, %x
+ %t3 = add i32 %nbits, 1
+ call void @use32(i32 %t0)
+ call void @use32(i32 %t1)
+ call void @use32(i32 %t2)
+ call void @use32(i32 %t3)
+ %t4 = shl i32 %t2, %t3
+ ret i32 %t4
+}
+
+; Vectors
+
+declare void @use3xi32(<3 x i32>)
+
+define <3 x i32> @t3_vec_splat(<3 x i32> %x, <3 x i32> %nbits) {
+; CHECK-LABEL: @t3_vec_splat(
+; CHECK-NEXT: [[T0:%.*]] = shl <3 x i32> <i32 -1, i32 -1, i32 -1>, [[NBITS:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = lshr <3 x i32> [[T0]], [[NBITS]]
+; CHECK-NEXT: [[T2:%.*]] = and <3 x i32> [[T1]], [[X:%.*]]
+; CHECK-NEXT: [[T3:%.*]] = add <3 x i32> [[NBITS]], <i32 1, i32 1, i32 1>
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T0]])
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T1]])
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T2]])
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T3]])
+; CHECK-NEXT: [[T4:%.*]] = shl <3 x i32> [[T2]], [[T3]]
+; CHECK-NEXT: ret <3 x i32> [[T4]]
+;
+ %t0 = shl <3 x i32> <i32 -1, i32 -1, i32 -1>, %nbits
+ %t1 = lshr <3 x i32> %t0, %nbits
+ %t2 = and <3 x i32> %t1, %x
+ %t3 = add <3 x i32> %nbits, <i32 1, i32 1, i32 1>
+ call void @use3xi32(<3 x i32> %t0)
+ call void @use3xi32(<3 x i32> %t1)
+ call void @use3xi32(<3 x i32> %t2)
+ call void @use3xi32(<3 x i32> %t3)
+ %t4 = shl <3 x i32> %t2, %t3
+ ret <3 x i32> %t4
+}
+
+define <3 x i32> @t4_vec_nonsplat(<3 x i32> %x, <3 x i32> %nbits) {
+; CHECK-LABEL: @t4_vec_nonsplat(
+; CHECK-NEXT: [[T0:%.*]] = shl <3 x i32> <i32 -1, i32 -1, i32 -1>, [[NBITS:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = lshr <3 x i32> [[T0]], [[NBITS]]
+; CHECK-NEXT: [[T2:%.*]] = and <3 x i32> [[T1]], [[X:%.*]]
+; CHECK-NEXT: [[T3:%.*]] = add <3 x i32> [[NBITS]], <i32 1, i32 0, i32 2>
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T0]])
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T1]])
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T2]])
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T3]])
+; CHECK-NEXT: [[T4:%.*]] = shl <3 x i32> [[T2]], [[T3]]
+; CHECK-NEXT: ret <3 x i32> [[T4]]
+;
+ %t0 = shl <3 x i32> <i32 -1, i32 -1, i32 -1>, %nbits
+ %t1 = lshr <3 x i32> %t0, %nbits
+ %t2 = and <3 x i32> %t1, %x
+ %t3 = add <3 x i32> %nbits, <i32 1, i32 0, i32 2>
+ call void @use3xi32(<3 x i32> %t0)
+ call void @use3xi32(<3 x i32> %t1)
+ call void @use3xi32(<3 x i32> %t2)
+ call void @use3xi32(<3 x i32> %t3)
+ %t4 = shl <3 x i32> %t2, %t3
+ ret <3 x i32> %t4
+}
+
+define <3 x i32> @t5_vec_undef(<3 x i32> %x, <3 x i32> %nbits) {
+; CHECK-LABEL: @t5_vec_undef(
+; CHECK-NEXT: [[T0:%.*]] = shl <3 x i32> <i32 -1, i32 undef, i32 -1>, [[NBITS:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = lshr <3 x i32> [[T0]], [[NBITS]]
+; CHECK-NEXT: [[T2:%.*]] = and <3 x i32> [[T1]], [[X:%.*]]
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T0]])
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T1]])
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T2]])
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[NBITS]])
+; CHECK-NEXT: [[T4:%.*]] = shl <3 x i32> [[T2]], [[NBITS]]
+; CHECK-NEXT: ret <3 x i32> [[T4]]
+;
+ %t0 = shl <3 x i32> <i32 -1, i32 undef, i32 -1>, %nbits
+ %t1 = lshr <3 x i32> %t0, %nbits
+ %t2 = and <3 x i32> %t1, %x
+ %t3 = add <3 x i32> %nbits, <i32 0, i32 undef, i32 0>
+ call void @use3xi32(<3 x i32> %t0)
+ call void @use3xi32(<3 x i32> %t1)
+ call void @use3xi32(<3 x i32> %t2)
+ call void @use3xi32(<3 x i32> %t3)
+ %t4 = shl <3 x i32> %t2, %t3
+ ret <3 x i32> %t4
+}
+
+; Commutativity
+
+declare i32 @gen32()
+
+define i32 @t6_commutativity0(i32 %nbits) {
+; CHECK-LABEL: @t6_commutativity0(
+; CHECK-NEXT: [[X:%.*]] = call i32 @gen32()
+; CHECK-NEXT: [[T0:%.*]] = shl i32 -1, [[NBITS:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = lshr i32 [[T0]], [[NBITS]]
+; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], [[T1]]
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: call void @use32(i32 [[T2]])
+; CHECK-NEXT: [[T3:%.*]] = shl i32 [[T2]], [[NBITS]]
+; CHECK-NEXT: ret i32 [[T3]]
+;
+ %x = call i32 @gen32()
+ %t0 = shl i32 -1, %nbits
+ %t1 = lshr i32 %t0, %nbits
+ %t2 = and i32 %x, %t1 ; swapped order
+ call void @use32(i32 %t0)
+ call void @use32(i32 %t1)
+ call void @use32(i32 %t2)
+ %t3 = shl i32 %t2, %nbits
+ ret i32 %t3
+}
+
+define i32 @t6_commutativity1(i32 %nbits0, i32 %nbits1) {
+; CHECK-LABEL: @t6_commutativity1(
+; CHECK-NEXT: [[T0:%.*]] = shl i32 -1, [[NBITS0:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = lshr i32 [[T0]], [[NBITS0]]
+; CHECK-NEXT: [[T2:%.*]] = shl i32 -1, [[NBITS0]]
+; CHECK-NEXT: [[T3:%.*]] = lshr i32 [[T0]], [[NBITS1:%.*]]
+; CHECK-NEXT: [[T4:%.*]] = and i32 [[T3]], [[T1]]
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: call void @use32(i32 [[T2]])
+; CHECK-NEXT: call void @use32(i32 [[T3]])
+; CHECK-NEXT: call void @use32(i32 [[T4]])
+; CHECK-NEXT: [[T5:%.*]] = shl i32 [[T4]], [[NBITS0]]
+; CHECK-NEXT: ret i32 [[T5]]
+;
+ %t0 = shl i32 -1, %nbits0
+ %t1 = lshr i32 %t0, %nbits0
+ %t2 = shl i32 -1, %nbits0
+ %t3 = lshr i32 %t0, %nbits1
+ %t4 = and i32 %t3, %t1 ; both hands of 'and' could be mask..
+ call void @use32(i32 %t0)
+ call void @use32(i32 %t1)
+ call void @use32(i32 %t2)
+ call void @use32(i32 %t3)
+ call void @use32(i32 %t4)
+ %t5 = shl i32 %t4, %nbits0
+ ret i32 %t5
+}
+define i32 @t6_commutativity2(i32 %nbits0, i32 %nbits1) {
+; CHECK-LABEL: @t6_commutativity2(
+; CHECK-NEXT: [[T0:%.*]] = shl i32 -1, [[NBITS0:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = lshr i32 [[T0]], [[NBITS0]]
+; CHECK-NEXT: [[T2:%.*]] = shl i32 -1, [[NBITS0]]
+; CHECK-NEXT: [[T3:%.*]] = lshr i32 [[T0]], [[NBITS1:%.*]]
+; CHECK-NEXT: [[T4:%.*]] = and i32 [[T3]], [[T1]]
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: call void @use32(i32 [[T2]])
+; CHECK-NEXT: call void @use32(i32 [[T3]])
+; CHECK-NEXT: call void @use32(i32 [[T4]])
+; CHECK-NEXT: [[T5:%.*]] = shl i32 [[T4]], [[NBITS1]]
+; CHECK-NEXT: ret i32 [[T5]]
+;
+ %t0 = shl i32 -1, %nbits0
+ %t1 = lshr i32 %t0, %nbits0
+ %t2 = shl i32 -1, %nbits0
+ %t3 = lshr i32 %t0, %nbits1
+ %t4 = and i32 %t3, %t1 ; both hands of 'and' could be mask..
+ call void @use32(i32 %t0)
+ call void @use32(i32 %t1)
+ call void @use32(i32 %t2)
+ call void @use32(i32 %t3)
+ call void @use32(i32 %t4)
+ %t5 = shl i32 %t4, %nbits1
+ ret i32 %t5
+}
+
+; Fast-math flags. We must not preserve them!
+
+define i32 @t7_nuw(i32 %x, i32 %nbits) {
+; CHECK-LABEL: @t7_nuw(
+; CHECK-NEXT: [[T0:%.*]] = shl i32 -1, [[NBITS:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = lshr i32 [[T0]], [[NBITS]]
+; CHECK-NEXT: [[T2:%.*]] = and i32 [[T1]], [[X:%.*]]
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: call void @use32(i32 [[T2]])
+; CHECK-NEXT: [[T3:%.*]] = shl nuw i32 [[T2]], [[NBITS]]
+; CHECK-NEXT: ret i32 [[T3]]
+;
+ %t0 = shl i32 -1, %nbits
+ %t1 = lshr i32 %t0, %nbits
+ %t2 = and i32 %t1, %x
+ call void @use32(i32 %t0)
+ call void @use32(i32 %t1)
+ call void @use32(i32 %t2)
+ %t3 = shl nuw i32 %t2, %nbits
+ ret i32 %t3
+}
+
+define i32 @t8_nsw(i32 %x, i32 %nbits) {
+; CHECK-LABEL: @t8_nsw(
+; CHECK-NEXT: [[T0:%.*]] = shl i32 -1, [[NBITS:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = lshr i32 [[T0]], [[NBITS]]
+; CHECK-NEXT: [[T2:%.*]] = and i32 [[T1]], [[X:%.*]]
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: call void @use32(i32 [[T2]])
+; CHECK-NEXT: [[T3:%.*]] = shl nsw i32 [[T2]], [[NBITS]]
+; CHECK-NEXT: ret i32 [[T3]]
+;
+ %t0 = shl i32 -1, %nbits
+ %t1 = lshr i32 %t0, %nbits
+ %t2 = and i32 %t1, %x
+ call void @use32(i32 %t0)
+ call void @use32(i32 %t1)
+ call void @use32(i32 %t2)
+ %t3 = shl nsw i32 %t2, %nbits
+ ret i32 %t3
+}
+
+define i32 @t9_nuw_nsw(i32 %x, i32 %nbits) {
+; CHECK-LABEL: @t9_nuw_nsw(
+; CHECK-NEXT: [[T0:%.*]] = shl i32 -1, [[NBITS:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = lshr i32 [[T0]], [[NBITS]]
+; CHECK-NEXT: [[T2:%.*]] = and i32 [[T1]], [[X:%.*]]
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: call void @use32(i32 [[T2]])
+; CHECK-NEXT: [[T3:%.*]] = shl nuw nsw i32 [[T2]], [[NBITS]]
+; CHECK-NEXT: ret i32 [[T3]]
+;
+ %t0 = shl i32 -1, %nbits
+ %t1 = lshr i32 %t0, %nbits
+ %t2 = and i32 %t1, %x
+ call void @use32(i32 %t0)
+ call void @use32(i32 %t1)
+ call void @use32(i32 %t2)
+ %t3 = shl nuw nsw i32 %t2, %nbits
+ ret i32 %t3
+}
+
+; Negative tests
+
+define i32 @n10(i32 %x, i32 %nbits) {
+; CHECK-LABEL: @n10(
+; CHECK-NEXT: [[T0:%.*]] = shl i32 -2, [[NBITS:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = lshr i32 [[T0]], [[NBITS]]
+; CHECK-NEXT: [[T2:%.*]] = and i32 [[T1]], [[X:%.*]]
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: call void @use32(i32 [[T2]])
+; CHECK-NEXT: [[T3:%.*]] = shl i32 [[T2]], [[NBITS]]
+; CHECK-NEXT: ret i32 [[T3]]
+;
+ %t0 = shl i32 -2, %nbits ; shifting not '-1'
+ %t1 = lshr i32 %t0, %nbits
+ %t2 = and i32 %t1, %x
+ call void @use32(i32 %t0)
+ call void @use32(i32 %t1)
+ call void @use32(i32 %t2)
+ %t3 = shl i32 %t2, %nbits
+ ret i32 %t3
+}
+
+define i32 @n11(i32 %x, i32 %nbits) {
+; CHECK-LABEL: @n11(
+; CHECK-NEXT: [[T0:%.*]] = shl i32 -1, [[NBITS:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = lshr i32 [[T0]], [[NBITS]]
+; CHECK-NEXT: [[T2:%.*]] = and i32 [[T1]], [[X:%.*]]
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: call void @use32(i32 [[T2]])
+; CHECK-NEXT: [[T4:%.*]] = shl i32 [[T2]], [[NBITS]]
+; CHECK-NEXT: ret i32 [[T4]]
+;
+ %t0 = shl i32 -1, %nbits
+ %t1 = lshr i32 %t0, %nbits
+ %t2 = and i32 %t1, %x
+ %t3 = add i32 %nbits, -1 ; shift is smaller than mask
+ call void @use32(i32 %t0)
+ call void @use32(i32 %t1)
+ call void @use32(i32 %t2)
+ %t4 = shl i32 %t2, %nbits
+ ret i32 %t4
+}
Added: llvm/trunk/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-e.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-e.ll?rev=365641&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-e.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-e.ll Wed Jul 10 08:08:06 2019
@@ -0,0 +1,213 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt %s -instcombine -S | FileCheck %s
+
+; If we have some pattern that leaves only some low bits set, and then performs
+; left-shift of those bits, if none of the bits that are left after the final
+; shift are modified by the mask, we can omit the mask.
+
+; There are many variants to this pattern:
+; e) ((x << maskNbits) l>> maskNbits) << shiftNbits
+; simplify to:
+; x << shiftNbits
+; iff (shiftNbits-maskNbits) s>= 0 (i.e. shiftNbits u>= maskNbits)
+
+; Simple tests. We don't care about extra uses.
+
+declare void @use32(i32)
+
+define i32 @t0_basic(i32 %x, i32 %nbits) {
+; CHECK-LABEL: @t0_basic(
+; CHECK-NEXT: [[T0:%.*]] = shl i32 [[X:%.*]], [[NBITS:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = lshr i32 [[T0]], [[NBITS]]
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: [[T2:%.*]] = shl i32 [[T1]], [[NBITS]]
+; CHECK-NEXT: ret i32 [[T2]]
+;
+ %t0 = shl i32 %x, %nbits
+ %t1 = lshr i32 %t0, %nbits
+ call void @use32(i32 %t0)
+ call void @use32(i32 %t1)
+ %t2 = shl i32 %t1, %nbits
+ ret i32 %t2
+}
+
+define i32 @t1_bigger_shift(i32 %x, i32 %nbits) {
+; CHECK-LABEL: @t1_bigger_shift(
+; CHECK-NEXT: [[T0:%.*]] = shl i32 [[X:%.*]], [[NBITS:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = lshr i32 [[T0]], [[NBITS]]
+; CHECK-NEXT: [[T2:%.*]] = add i32 [[NBITS]], 1
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: call void @use32(i32 [[T2]])
+; CHECK-NEXT: [[T3:%.*]] = shl i32 [[T1]], [[T2]]
+; CHECK-NEXT: ret i32 [[T3]]
+;
+ %t0 = shl i32 %x, %nbits
+ %t1 = lshr i32 %t0, %nbits
+ %t2 = add i32 %nbits, 1
+ call void @use32(i32 %t0)
+ call void @use32(i32 %t1)
+ call void @use32(i32 %t2)
+ %t3 = shl i32 %t1, %t2
+ ret i32 %t3
+}
+
+; Vectors
+
+declare void @use3xi32(<3 x i32>)
+
+define <3 x i32> @t2_vec_splat(<3 x i32> %x, <3 x i32> %nbits) {
+; CHECK-LABEL: @t2_vec_splat(
+; CHECK-NEXT: [[T0:%.*]] = shl <3 x i32> [[X:%.*]], [[NBITS:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = lshr <3 x i32> [[T0]], [[NBITS]]
+; CHECK-NEXT: [[T2:%.*]] = add <3 x i32> [[NBITS]], <i32 1, i32 1, i32 1>
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T0]])
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T1]])
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T2]])
+; CHECK-NEXT: [[T3:%.*]] = shl <3 x i32> [[T1]], [[T2]]
+; CHECK-NEXT: ret <3 x i32> [[T3]]
+;
+ %t0 = shl <3 x i32> %x, %nbits
+ %t1 = lshr <3 x i32> %t0, %nbits
+ %t2 = add <3 x i32> %nbits, <i32 1, i32 1, i32 1>
+ call void @use3xi32(<3 x i32> %t0)
+ call void @use3xi32(<3 x i32> %t1)
+ call void @use3xi32(<3 x i32> %t2)
+ %t3 = shl <3 x i32> %t1, %t2
+ ret <3 x i32> %t3
+}
+
+define <3 x i32> @t3_vec_nonsplat(<3 x i32> %x, <3 x i32> %nbits) {
+; CHECK-LABEL: @t3_vec_nonsplat(
+; CHECK-NEXT: [[T0:%.*]] = shl <3 x i32> [[X:%.*]], [[NBITS:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = lshr <3 x i32> [[T0]], [[NBITS]]
+; CHECK-NEXT: [[T2:%.*]] = add <3 x i32> [[NBITS]], <i32 1, i32 0, i32 2>
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T0]])
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T1]])
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T2]])
+; CHECK-NEXT: [[T3:%.*]] = shl <3 x i32> [[T1]], [[T2]]
+; CHECK-NEXT: ret <3 x i32> [[T3]]
+;
+ %t0 = shl <3 x i32> %x, %nbits
+ %t1 = lshr <3 x i32> %t0, %nbits
+ %t2 = add <3 x i32> %nbits, <i32 1, i32 0, i32 2>
+ call void @use3xi32(<3 x i32> %t0)
+ call void @use3xi32(<3 x i32> %t1)
+ call void @use3xi32(<3 x i32> %t2)
+ %t3 = shl <3 x i32> %t1, %t2
+ ret <3 x i32> %t3
+}
+
+define <3 x i32> @t4_vec_undef(<3 x i32> %x, <3 x i32> %nbits) {
+; CHECK-LABEL: @t4_vec_undef(
+; CHECK-NEXT: [[T0:%.*]] = shl <3 x i32> [[X:%.*]], [[NBITS:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = lshr <3 x i32> [[T0]], [[NBITS]]
+; CHECK-NEXT: [[T2:%.*]] = add <3 x i32> [[NBITS]], <i32 1, i32 undef, i32 1>
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T0]])
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T1]])
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T2]])
+; CHECK-NEXT: [[T3:%.*]] = shl <3 x i32> [[T1]], [[T2]]
+; CHECK-NEXT: ret <3 x i32> [[T3]]
+;
+ %t0 = shl <3 x i32> %x, %nbits
+ %t1 = lshr <3 x i32> %t0, %nbits
+ %t2 = add <3 x i32> %nbits, <i32 1, i32 undef, i32 1>
+ call void @use3xi32(<3 x i32> %t0)
+ call void @use3xi32(<3 x i32> %t1)
+ call void @use3xi32(<3 x i32> %t2)
+ %t3 = shl <3 x i32> %t1, %t2
+ ret <3 x i32> %t3
+}
+
+; Fast-math flags. We must not preserve them!
+
+define i32 @t8_nuw(i32 %x, i32 %nbits) {
+; CHECK-LABEL: @t8_nuw(
+; CHECK-NEXT: [[T0:%.*]] = shl i32 [[X:%.*]], [[NBITS:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = lshr i32 [[T0]], [[NBITS]]
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: [[T2:%.*]] = shl nuw i32 [[T1]], [[NBITS]]
+; CHECK-NEXT: ret i32 [[T2]]
+;
+ %t0 = shl i32 %x, %nbits
+ %t1 = lshr i32 %t0, %nbits
+ call void @use32(i32 %t0)
+ call void @use32(i32 %t1)
+ %t2 = shl nuw i32 %t1, %nbits
+ ret i32 %t2
+}
+
+define i32 @t9_nsw(i32 %x, i32 %nbits) {
+; CHECK-LABEL: @t9_nsw(
+; CHECK-NEXT: [[T0:%.*]] = shl i32 [[X:%.*]], [[NBITS:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = lshr i32 [[T0]], [[NBITS]]
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: [[T2:%.*]] = shl nsw i32 [[T1]], [[NBITS]]
+; CHECK-NEXT: ret i32 [[T2]]
+;
+ %t0 = shl i32 %x, %nbits
+ %t1 = lshr i32 %t0, %nbits
+ call void @use32(i32 %t0)
+ call void @use32(i32 %t1)
+ %t2 = shl nsw i32 %t1, %nbits
+ ret i32 %t2
+}
+
+define i32 @t10_nuw_nsw(i32 %x, i32 %nbits) {
+; CHECK-LABEL: @t10_nuw_nsw(
+; CHECK-NEXT: [[T0:%.*]] = shl i32 [[X:%.*]], [[NBITS:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = lshr i32 [[T0]], [[NBITS]]
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: [[T2:%.*]] = shl nuw nsw i32 [[T1]], [[NBITS]]
+; CHECK-NEXT: ret i32 [[T2]]
+;
+ %t0 = shl i32 %x, %nbits
+ %t1 = lshr i32 %t0, %nbits
+ call void @use32(i32 %t0)
+ call void @use32(i32 %t1)
+ %t2 = shl nuw nsw i32 %t1, %nbits
+ ret i32 %t2
+}
+
+; Negative tests
+
+define i32 @n11(i32 %x, i32 %nbits) {
+; CHECK-LABEL: @n11(
+; CHECK-NEXT: [[T0:%.*]] = shl i32 -2, [[NBITS:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = lshr i32 [[T0]], [[NBITS]]
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: [[T2:%.*]] = shl i32 [[T1]], [[NBITS]]
+; CHECK-NEXT: ret i32 [[T2]]
+;
+ %t0 = shl i32 -2, %nbits ; shifting not '-1'
+ %t1 = lshr i32 %t0, %nbits
+ call void @use32(i32 %t0)
+ call void @use32(i32 %t1)
+ %t2 = shl i32 %t1, %nbits
+ ret i32 %t2
+}
+
+define i32 @n12(i32 %x, i32 %nbits) {
+; CHECK-LABEL: @n12(
+; CHECK-NEXT: [[T0:%.*]] = shl i32 [[X:%.*]], [[NBITS:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = lshr i32 [[T0]], [[NBITS]]
+; CHECK-NEXT: [[T2:%.*]] = add i32 [[NBITS]], -1
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: call void @use32(i32 [[T2]])
+; CHECK-NEXT: ret i32 [[T2]]
+;
+ %t0 = shl i32 %x, %nbits
+ %t1 = lshr i32 %t0, %nbits
+ %t2 = add i32 %nbits, -1
+ call void @use32(i32 %t0)
+ call void @use32(i32 %t1)
+ call void @use32(i32 %t2)
+ %t3 = shl i32 %t1, %t2 ; shift is smaller than mask
+ ret i32 %t2
+}
Added: llvm/trunk/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-f.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-f.ll?rev=365641&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-f.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-f.ll Wed Jul 10 08:08:06 2019
@@ -0,0 +1,213 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt %s -instcombine -S | FileCheck %s
+
+; If we have some pattern that leaves only some low bits set, and then performs
+; left-shift of those bits, if none of the bits that are left after the final
+; shift are modified by the mask, we can omit the mask.
+
+; There are many variants to this pattern:
+; f) ((x << maskNbits) a>> maskNbits) << shiftNbits
+; simplify to:
+; x << shiftNbits
+; iff (shiftNbits-maskNbits) s>= 0 (i.e. shiftNbits u>= maskNbits)
+
+; Simple tests. We don't care about extra uses.
+
+declare void @use32(i32)
+
+define i32 @t0_basic(i32 %x, i32 %nbits) {
+; CHECK-LABEL: @t0_basic(
+; CHECK-NEXT: [[T0:%.*]] = shl i32 [[X:%.*]], [[NBITS:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = ashr i32 [[T0]], [[NBITS]]
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: [[T2:%.*]] = shl i32 [[T1]], [[NBITS]]
+; CHECK-NEXT: ret i32 [[T2]]
+;
+ %t0 = shl i32 %x, %nbits
+ %t1 = ashr i32 %t0, %nbits
+ call void @use32(i32 %t0)
+ call void @use32(i32 %t1)
+ %t2 = shl i32 %t1, %nbits
+ ret i32 %t2
+}
+
+define i32 @t1_bigger_shift(i32 %x, i32 %nbits) {
+; CHECK-LABEL: @t1_bigger_shift(
+; CHECK-NEXT: [[T0:%.*]] = shl i32 [[X:%.*]], [[NBITS:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = ashr i32 [[T0]], [[NBITS]]
+; CHECK-NEXT: [[T2:%.*]] = add i32 [[NBITS]], 1
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: call void @use32(i32 [[T2]])
+; CHECK-NEXT: [[T3:%.*]] = shl i32 [[T1]], [[T2]]
+; CHECK-NEXT: ret i32 [[T3]]
+;
+ %t0 = shl i32 %x, %nbits
+ %t1 = ashr i32 %t0, %nbits
+ %t2 = add i32 %nbits, 1
+ call void @use32(i32 %t0)
+ call void @use32(i32 %t1)
+ call void @use32(i32 %t2)
+ %t3 = shl i32 %t1, %t2
+ ret i32 %t3
+}
+
+; Vectors
+
+declare void @use3xi32(<3 x i32>)
+
+define <3 x i32> @t2_vec_splat(<3 x i32> %x, <3 x i32> %nbits) {
+; CHECK-LABEL: @t2_vec_splat(
+; CHECK-NEXT: [[T0:%.*]] = shl <3 x i32> [[X:%.*]], [[NBITS:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = ashr <3 x i32> [[T0]], [[NBITS]]
+; CHECK-NEXT: [[T2:%.*]] = add <3 x i32> [[NBITS]], <i32 1, i32 1, i32 1>
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T0]])
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T1]])
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T2]])
+; CHECK-NEXT: [[T3:%.*]] = shl <3 x i32> [[T1]], [[T2]]
+; CHECK-NEXT: ret <3 x i32> [[T3]]
+;
+ %t0 = shl <3 x i32> %x, %nbits
+ %t1 = ashr <3 x i32> %t0, %nbits
+ %t2 = add <3 x i32> %nbits, <i32 1, i32 1, i32 1>
+ call void @use3xi32(<3 x i32> %t0)
+ call void @use3xi32(<3 x i32> %t1)
+ call void @use3xi32(<3 x i32> %t2)
+ %t3 = shl <3 x i32> %t1, %t2
+ ret <3 x i32> %t3
+}
+
+define <3 x i32> @t3_vec_nonsplat(<3 x i32> %x, <3 x i32> %nbits) {
+; CHECK-LABEL: @t3_vec_nonsplat(
+; CHECK-NEXT: [[T0:%.*]] = shl <3 x i32> [[X:%.*]], [[NBITS:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = ashr <3 x i32> [[T0]], [[NBITS]]
+; CHECK-NEXT: [[T2:%.*]] = add <3 x i32> [[NBITS]], <i32 1, i32 0, i32 2>
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T0]])
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T1]])
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T2]])
+; CHECK-NEXT: [[T3:%.*]] = shl <3 x i32> [[T1]], [[T2]]
+; CHECK-NEXT: ret <3 x i32> [[T3]]
+;
+ %t0 = shl <3 x i32> %x, %nbits
+ %t1 = ashr <3 x i32> %t0, %nbits
+ %t2 = add <3 x i32> %nbits, <i32 1, i32 0, i32 2>
+ call void @use3xi32(<3 x i32> %t0)
+ call void @use3xi32(<3 x i32> %t1)
+ call void @use3xi32(<3 x i32> %t2)
+ %t3 = shl <3 x i32> %t1, %t2
+ ret <3 x i32> %t3
+}
+
+define <3 x i32> @t4_vec_undef(<3 x i32> %x, <3 x i32> %nbits) {
+; CHECK-LABEL: @t4_vec_undef(
+; CHECK-NEXT: [[T0:%.*]] = shl <3 x i32> [[X:%.*]], [[NBITS:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = ashr <3 x i32> [[T0]], [[NBITS]]
+; CHECK-NEXT: [[T2:%.*]] = add <3 x i32> [[NBITS]], <i32 1, i32 undef, i32 1>
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T0]])
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T1]])
+; CHECK-NEXT: call void @use3xi32(<3 x i32> [[T2]])
+; CHECK-NEXT: [[T3:%.*]] = shl <3 x i32> [[T1]], [[T2]]
+; CHECK-NEXT: ret <3 x i32> [[T3]]
+;
+ %t0 = shl <3 x i32> %x, %nbits
+ %t1 = ashr <3 x i32> %t0, %nbits
+ %t2 = add <3 x i32> %nbits, <i32 1, i32 undef, i32 1>
+ call void @use3xi32(<3 x i32> %t0)
+ call void @use3xi32(<3 x i32> %t1)
+ call void @use3xi32(<3 x i32> %t2)
+ %t3 = shl <3 x i32> %t1, %t2
+ ret <3 x i32> %t3
+}
+
+; Fast-math flags. We must not preserve them!
+
+define i32 @t8_nuw(i32 %x, i32 %nbits) {
+; CHECK-LABEL: @t8_nuw(
+; CHECK-NEXT: [[T0:%.*]] = shl i32 [[X:%.*]], [[NBITS:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = ashr i32 [[T0]], [[NBITS]]
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: [[T2:%.*]] = shl nuw i32 [[T1]], [[NBITS]]
+; CHECK-NEXT: ret i32 [[T2]]
+;
+ %t0 = shl i32 %x, %nbits
+ %t1 = ashr i32 %t0, %nbits
+ call void @use32(i32 %t0)
+ call void @use32(i32 %t1)
+ %t2 = shl nuw i32 %t1, %nbits
+ ret i32 %t2
+}
+
+define i32 @t9_nsw(i32 %x, i32 %nbits) {
+; CHECK-LABEL: @t9_nsw(
+; CHECK-NEXT: [[T0:%.*]] = shl i32 [[X:%.*]], [[NBITS:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = ashr i32 [[T0]], [[NBITS]]
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: [[T2:%.*]] = shl nsw i32 [[T1]], [[NBITS]]
+; CHECK-NEXT: ret i32 [[T2]]
+;
+ %t0 = shl i32 %x, %nbits
+ %t1 = ashr i32 %t0, %nbits
+ call void @use32(i32 %t0)
+ call void @use32(i32 %t1)
+ %t2 = shl nsw i32 %t1, %nbits
+ ret i32 %t2
+}
+
+define i32 @t10_nuw_nsw(i32 %x, i32 %nbits) {
+; CHECK-LABEL: @t10_nuw_nsw(
+; CHECK-NEXT: [[T0:%.*]] = shl i32 [[X:%.*]], [[NBITS:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = ashr i32 [[T0]], [[NBITS]]
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: [[T2:%.*]] = shl nuw nsw i32 [[T1]], [[NBITS]]
+; CHECK-NEXT: ret i32 [[T2]]
+;
+ %t0 = shl i32 %x, %nbits
+ %t1 = ashr i32 %t0, %nbits
+ call void @use32(i32 %t0)
+ call void @use32(i32 %t1)
+ %t2 = shl nuw nsw i32 %t1, %nbits
+ ret i32 %t2
+}
+
+; Negative tests
+
+define i32 @n11(i32 %x, i32 %nbits) {
+; CHECK-LABEL: @n11(
+; CHECK-NEXT: [[T0:%.*]] = shl i32 -2, [[NBITS:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = ashr i32 [[T0]], [[NBITS]]
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: [[T2:%.*]] = shl i32 [[T1]], [[NBITS]]
+; CHECK-NEXT: ret i32 [[T2]]
+;
+ %t0 = shl i32 -2, %nbits ; shifting not '-1'
+ %t1 = ashr i32 %t0, %nbits
+ call void @use32(i32 %t0)
+ call void @use32(i32 %t1)
+ %t2 = shl i32 %t1, %nbits
+ ret i32 %t2
+}
+
+define i32 @n12(i32 %x, i32 %nbits) {
+; CHECK-LABEL: @n12(
+; CHECK-NEXT: [[T0:%.*]] = shl i32 [[X:%.*]], [[NBITS:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = ashr i32 [[T0]], [[NBITS]]
+; CHECK-NEXT: [[T2:%.*]] = add i32 [[NBITS]], -1
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: call void @use32(i32 [[T2]])
+; CHECK-NEXT: ret i32 [[T2]]
+;
+ %t0 = shl i32 %x, %nbits
+ %t1 = ashr i32 %t0, %nbits
+ %t2 = add i32 %nbits, -1
+ call void @use32(i32 %t0)
+ call void @use32(i32 %t1)
+ call void @use32(i32 %t2)
+ %t3 = shl i32 %t1, %t2 ; shift is smaller than mask
+ ret i32 %t2
+}
Added: llvm/trunk/test/Transforms/InstCombine/redundant-right-shift-input-masking.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/redundant-right-shift-input-masking.ll?rev=365641&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/redundant-right-shift-input-masking.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/redundant-right-shift-input-masking.ll Wed Jul 10 08:08:06 2019
@@ -0,0 +1,249 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt %s -instcombine -S | FileCheck %s
+
+; If we have:
+; (data & (-1 << nbits)) outer>> nbits
+; Or
+; ((data inner>> nbits) << nbits) outer>> nbits
+; The mask is redundant, and can be dropped:
+; data outer>> nbits
+; This is valid for both lshr and ashr in both positions and any combination.
+; We must *not* preserve 'exact' on that final right-shift.
+
+define i32 @t0_lshr(i32 %data, i32 %nbits) {
+; CHECK-LABEL: @t0_lshr(
+; CHECK-NEXT: [[T0:%.*]] = shl i32 -1, [[NBITS:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[DATA:%.*]]
+; CHECK-NEXT: [[T2:%.*]] = lshr exact i32 [[T1]], [[NBITS]]
+; CHECK-NEXT: ret i32 [[T2]]
+;
+ %t0 = shl i32 -1, %nbits
+ %t1 = and i32 %t0, %data
+ %t2 = lshr exact i32 %t1, %nbits ; while there, test that we *don't* propagate 'exact'
+ ret i32 %t2
+}
+define i32 @t1_sshr(i32 %data, i32 %nbits) {
+; CHECK-LABEL: @t1_sshr(
+; CHECK-NEXT: [[T0:%.*]] = shl i32 -1, [[NBITS:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[DATA:%.*]]
+; CHECK-NEXT: [[T2:%.*]] = ashr exact i32 [[T1]], [[NBITS]]
+; CHECK-NEXT: ret i32 [[T2]]
+;
+ %t0 = shl i32 -1, %nbits
+ %t1 = and i32 %t0, %data
+ %t2 = ashr exact i32 %t1, %nbits ; while there, test that we *don't* propagate 'exact'
+ ret i32 %t2
+}
+
+; Vectors
+
+define <4 x i32> @t2_vec(<4 x i32> %data, <4 x i32> %nbits) {
+; CHECK-LABEL: @t2_vec(
+; CHECK-NEXT: [[T0:%.*]] = shl <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, [[NBITS:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = and <4 x i32> [[T0]], [[DATA:%.*]]
+; CHECK-NEXT: [[T2:%.*]] = lshr <4 x i32> [[T1]], [[NBITS]]
+; CHECK-NEXT: ret <4 x i32> [[T2]]
+;
+ %t0 = shl <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, %nbits
+ %t1 = and <4 x i32> %t0, %data
+ %t2 = lshr <4 x i32> %t1, %nbits
+ ret <4 x i32> %t2
+}
+
+define <4 x i32> @t3_vec_undef(<4 x i32> %data, <4 x i32> %nbits) {
+; CHECK-LABEL: @t3_vec_undef(
+; CHECK-NEXT: [[T0:%.*]] = shl <4 x i32> <i32 -1, i32 -1, i32 undef, i32 -1>, [[NBITS:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = and <4 x i32> [[T0]], [[DATA:%.*]]
+; CHECK-NEXT: [[T2:%.*]] = lshr <4 x i32> [[T1]], [[NBITS]]
+; CHECK-NEXT: ret <4 x i32> [[T2]]
+;
+ %t0 = shl <4 x i32> <i32 -1, i32 -1, i32 undef, i32 -1>, %nbits
+ %t1 = and <4 x i32> %t0, %data
+ %t2 = lshr <4 x i32> %t1, %nbits
+ ret <4 x i32> %t2
+}
+
+; Extra uses
+
+declare void @use32(i32)
+
+define i32 @t4_extrause0(i32 %data, i32 %nbits) {
+; CHECK-LABEL: @t4_extrause0(
+; CHECK-NEXT: [[T0:%.*]] = shl i32 -1, [[NBITS:%.*]]
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[DATA:%.*]]
+; CHECK-NEXT: [[T2:%.*]] = lshr i32 [[T1]], [[NBITS]]
+; CHECK-NEXT: ret i32 [[T2]]
+;
+ %t0 = shl i32 -1, %nbits
+ call void @use32(i32 %t0)
+ %t1 = and i32 %t0, %data
+ %t2 = lshr i32 %t1, %nbits
+ ret i32 %t2
+}
+
+define i32 @t5_extrause1(i32 %data, i32 %nbits) {
+; CHECK-LABEL: @t5_extrause1(
+; CHECK-NEXT: [[T0:%.*]] = shl i32 -1, [[NBITS:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[DATA:%.*]]
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: [[T2:%.*]] = lshr i32 [[T1]], [[NBITS]]
+; CHECK-NEXT: ret i32 [[T2]]
+;
+ %t0 = shl i32 -1, %nbits
+ %t1 = and i32 %t0, %data
+ call void @use32(i32 %t1)
+ %t2 = lshr i32 %t1, %nbits
+ ret i32 %t2
+}
+
+define i32 @t6_extrause2(i32 %data, i32 %nbits) {
+; CHECK-LABEL: @t6_extrause2(
+; CHECK-NEXT: [[T0:%.*]] = shl i32 -1, [[NBITS:%.*]]
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[DATA:%.*]]
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: [[T2:%.*]] = lshr i32 [[T1]], [[NBITS]]
+; CHECK-NEXT: ret i32 [[T2]]
+;
+ %t0 = shl i32 -1, %nbits
+ call void @use32(i32 %t0)
+ %t1 = and i32 %t0, %data
+ call void @use32(i32 %t1)
+ %t2 = lshr i32 %t1, %nbits
+ ret i32 %t2
+}
+
+; Non-canonical mask pattern. Let's just test a single case with all-extra uses.
+
+define i32 @t7_noncanonical_lshr_lshr_extrauses(i32 %data, i32 %nbits) {
+; CHECK-LABEL: @t7_noncanonical_lshr_lshr_extrauses(
+; CHECK-NEXT: [[T0:%.*]] = lshr i32 [[DATA:%.*]], [[NBITS:%.*]]
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: [[T1:%.*]] = shl i32 [[T0]], [[NBITS]]
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: [[T2:%.*]] = lshr i32 [[T1]], [[NBITS]]
+; CHECK-NEXT: ret i32 [[T2]]
+;
+ %t0 = lshr i32 %data, %nbits
+ call void @use32(i32 %t0)
+ %t1 = shl i32 %t0, %nbits
+ call void @use32(i32 %t1)
+ %t2 = lshr i32 %t1, %nbits
+ ret i32 %t2
+}
+
+define i32 @t8_noncanonical_lshr_ashr_extrauses(i32 %data, i32 %nbits) {
+; CHECK-LABEL: @t8_noncanonical_lshr_ashr_extrauses(
+; CHECK-NEXT: [[T0:%.*]] = lshr i32 [[DATA:%.*]], [[NBITS:%.*]]
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: [[T1:%.*]] = shl i32 [[T0]], [[NBITS]]
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: [[T2:%.*]] = ashr i32 [[T1]], [[NBITS]]
+; CHECK-NEXT: ret i32 [[T2]]
+;
+ %t0 = lshr i32 %data, %nbits
+ call void @use32(i32 %t0)
+ %t1 = shl i32 %t0, %nbits
+ call void @use32(i32 %t1)
+ %t2 = ashr i32 %t1, %nbits
+ ret i32 %t2
+}
+
+define i32 @t9_noncanonical_ashr_lshr_extrauses(i32 %data, i32 %nbits) {
+; CHECK-LABEL: @t9_noncanonical_ashr_lshr_extrauses(
+; CHECK-NEXT: [[T0:%.*]] = ashr i32 [[DATA:%.*]], [[NBITS:%.*]]
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: [[T1:%.*]] = shl i32 [[T0]], [[NBITS]]
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: [[T2:%.*]] = lshr i32 [[T1]], [[NBITS]]
+; CHECK-NEXT: ret i32 [[T2]]
+;
+ %t0 = ashr i32 %data, %nbits
+ call void @use32(i32 %t0)
+ %t1 = shl i32 %t0, %nbits
+ call void @use32(i32 %t1)
+ %t2 = lshr i32 %t1, %nbits
+ ret i32 %t2
+}
+
+define i32 @t10_noncanonical_ashr_ashr_extrauses(i32 %data, i32 %nbits) {
+; CHECK-LABEL: @t10_noncanonical_ashr_ashr_extrauses(
+; CHECK-NEXT: [[T0:%.*]] = ashr i32 [[DATA:%.*]], [[NBITS:%.*]]
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: [[T1:%.*]] = shl i32 [[T0]], [[NBITS]]
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: [[T2:%.*]] = ashr i32 [[T1]], [[NBITS]]
+; CHECK-NEXT: ret i32 [[T2]]
+;
+ %t0 = ashr i32 %data, %nbits
+ call void @use32(i32 %t0)
+ %t1 = shl i32 %t0, %nbits
+ call void @use32(i32 %t1)
+ %t2 = ashr i32 %t1, %nbits
+ ret i32 %t2
+}
+
+; Commutativity
+
+declare i32 @gen32()
+
+define i32 @t11_commutative(i32 %nbits) {
+; CHECK-LABEL: @t11_commutative(
+; CHECK-NEXT: [[DATA:%.*]] = call i32 @gen32()
+; CHECK-NEXT: [[T0:%.*]] = shl i32 -1, [[NBITS:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = and i32 [[DATA]], [[T0]]
+; CHECK-NEXT: [[T2:%.*]] = lshr i32 [[T1]], [[NBITS]]
+; CHECK-NEXT: ret i32 [[T2]]
+;
+ %data = call i32 @gen32()
+ %t0 = shl i32 -1, %nbits
+ %t1 = and i32 %data, %t0 ; swapped
+ %t2 = lshr i32 %t1, %nbits
+ ret i32 %t2
+}
+
+; Negative tests
+
+define i32 @n12(i32 %data, i32 %nbits) {
+; CHECK-LABEL: @n12(
+; CHECK-NEXT: [[T0:%.*]] = shl i32 2147483647, [[NBITS:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[DATA:%.*]]
+; CHECK-NEXT: [[T2:%.*]] = lshr i32 [[T1]], [[NBITS]]
+; CHECK-NEXT: ret i32 [[T2]]
+;
+ %t0 = shl i32 2147483647, %nbits ; must be shifting -1
+ %t1 = and i32 %t0, %data
+ %t2 = lshr i32 %t1, %nbits
+ ret i32 %t2
+}
+
+define i32 @n13(i32 %data, i32 %nbits0, i32 %nbits1) {
+; CHECK-LABEL: @n13(
+; CHECK-NEXT: [[T0:%.*]] = shl i32 -1, [[NBITS0:%.*]]
+; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[DATA:%.*]]
+; CHECK-NEXT: [[T2:%.*]] = lshr i32 [[T1]], [[NBITS1:%.*]]
+; CHECK-NEXT: ret i32 [[T2]]
+;
+ %t0 = shl i32 -1, %nbits0
+ %t1 = and i32 %t0, %data
+ %t2 = lshr i32 %t1, %nbits1 ; different shift amounts
+ ret i32 %t2
+}
+
+define i32 @n14(i32 %data, i32 %nbits0, i32 %nbits1, i32 %nbits2) {
+; CHECK-LABEL: @n14(
+; CHECK-NEXT: [[T0:%.*]] = lshr i32 [[DATA:%.*]], [[NBITS0:%.*]]
+; CHECK-NEXT: call void @use32(i32 [[T0]])
+; CHECK-NEXT: [[T1:%.*]] = shl i32 [[T0]], [[NBITS1:%.*]]
+; CHECK-NEXT: call void @use32(i32 [[T1]])
+; CHECK-NEXT: [[T2:%.*]] = lshr i32 [[T1]], [[NBITS2:%.*]]
+; CHECK-NEXT: ret i32 [[T2]]
+;
+ %t0 = lshr i32 %data, %nbits0
+ call void @use32(i32 %t0)
+ %t1 = shl i32 %t0, %nbits1 ; different shift amounts
+ call void @use32(i32 %t1)
+ %t2 = lshr i32 %t1, %nbits2 ; different shift amounts
+ ret i32 %t2
+}
Removed: llvm/trunk/test/Transforms/InstCombine/redundant-shift-input-masking.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/redundant-shift-input-masking.ll?rev=365640&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/redundant-shift-input-masking.ll (original)
+++ llvm/trunk/test/Transforms/InstCombine/redundant-shift-input-masking.ll (removed)
@@ -1,249 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt %s -instcombine -S | FileCheck %s
-
-; If we have:
-; (data & (-1 << nbits)) outer>> nbits
-; Or
-; ((data inner>> nbits) << nbits) outer>> nbits
-; The mask is redundant, and can be dropped:
-; data outer>> nbits
-; This is valid for both lshr and ashr in both positions and any combination.
-; We must *not* preserve 'exact' on that final right-shift.
-
-define i32 @t0_lshr(i32 %data, i32 %nbits) {
-; CHECK-LABEL: @t0_lshr(
-; CHECK-NEXT: [[T0:%.*]] = shl i32 -1, [[NBITS:%.*]]
-; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[DATA:%.*]]
-; CHECK-NEXT: [[T2:%.*]] = lshr exact i32 [[T1]], [[NBITS]]
-; CHECK-NEXT: ret i32 [[T2]]
-;
- %t0 = shl i32 -1, %nbits
- %t1 = and i32 %t0, %data
- %t2 = lshr exact i32 %t1, %nbits ; while there, test that we *don't* propagate 'exact'
- ret i32 %t2
-}
-define i32 @t1_sshr(i32 %data, i32 %nbits) {
-; CHECK-LABEL: @t1_sshr(
-; CHECK-NEXT: [[T0:%.*]] = shl i32 -1, [[NBITS:%.*]]
-; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[DATA:%.*]]
-; CHECK-NEXT: [[T2:%.*]] = ashr exact i32 [[T1]], [[NBITS]]
-; CHECK-NEXT: ret i32 [[T2]]
-;
- %t0 = shl i32 -1, %nbits
- %t1 = and i32 %t0, %data
- %t2 = ashr exact i32 %t1, %nbits ; while there, test that we *don't* propagate 'exact'
- ret i32 %t2
-}
-
-; Vectors
-
-define <4 x i32> @t2_vec(<4 x i32> %data, <4 x i32> %nbits) {
-; CHECK-LABEL: @t2_vec(
-; CHECK-NEXT: [[T0:%.*]] = shl <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, [[NBITS:%.*]]
-; CHECK-NEXT: [[T1:%.*]] = and <4 x i32> [[T0]], [[DATA:%.*]]
-; CHECK-NEXT: [[T2:%.*]] = lshr <4 x i32> [[T1]], [[NBITS]]
-; CHECK-NEXT: ret <4 x i32> [[T2]]
-;
- %t0 = shl <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, %nbits
- %t1 = and <4 x i32> %t0, %data
- %t2 = lshr <4 x i32> %t1, %nbits
- ret <4 x i32> %t2
-}
-
-define <4 x i32> @t3_vec_undef(<4 x i32> %data, <4 x i32> %nbits) {
-; CHECK-LABEL: @t3_vec_undef(
-; CHECK-NEXT: [[T0:%.*]] = shl <4 x i32> <i32 -1, i32 -1, i32 undef, i32 -1>, [[NBITS:%.*]]
-; CHECK-NEXT: [[T1:%.*]] = and <4 x i32> [[T0]], [[DATA:%.*]]
-; CHECK-NEXT: [[T2:%.*]] = lshr <4 x i32> [[T1]], [[NBITS]]
-; CHECK-NEXT: ret <4 x i32> [[T2]]
-;
- %t0 = shl <4 x i32> <i32 -1, i32 -1, i32 undef, i32 -1>, %nbits
- %t1 = and <4 x i32> %t0, %data
- %t2 = lshr <4 x i32> %t1, %nbits
- ret <4 x i32> %t2
-}
-
-; Extra uses
-
-declare void @use32(i32)
-
-define i32 @t4_extrause0(i32 %data, i32 %nbits) {
-; CHECK-LABEL: @t4_extrause0(
-; CHECK-NEXT: [[T0:%.*]] = shl i32 -1, [[NBITS:%.*]]
-; CHECK-NEXT: call void @use32(i32 [[T0]])
-; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[DATA:%.*]]
-; CHECK-NEXT: [[T2:%.*]] = lshr i32 [[T1]], [[NBITS]]
-; CHECK-NEXT: ret i32 [[T2]]
-;
- %t0 = shl i32 -1, %nbits
- call void @use32(i32 %t0)
- %t1 = and i32 %t0, %data
- %t2 = lshr i32 %t1, %nbits
- ret i32 %t2
-}
-
-define i32 @t5_extrause1(i32 %data, i32 %nbits) {
-; CHECK-LABEL: @t5_extrause1(
-; CHECK-NEXT: [[T0:%.*]] = shl i32 -1, [[NBITS:%.*]]
-; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[DATA:%.*]]
-; CHECK-NEXT: call void @use32(i32 [[T1]])
-; CHECK-NEXT: [[T2:%.*]] = lshr i32 [[T1]], [[NBITS]]
-; CHECK-NEXT: ret i32 [[T2]]
-;
- %t0 = shl i32 -1, %nbits
- %t1 = and i32 %t0, %data
- call void @use32(i32 %t1)
- %t2 = lshr i32 %t1, %nbits
- ret i32 %t2
-}
-
-define i32 @t6_extrause2(i32 %data, i32 %nbits) {
-; CHECK-LABEL: @t6_extrause2(
-; CHECK-NEXT: [[T0:%.*]] = shl i32 -1, [[NBITS:%.*]]
-; CHECK-NEXT: call void @use32(i32 [[T0]])
-; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[DATA:%.*]]
-; CHECK-NEXT: call void @use32(i32 [[T1]])
-; CHECK-NEXT: [[T2:%.*]] = lshr i32 [[T1]], [[NBITS]]
-; CHECK-NEXT: ret i32 [[T2]]
-;
- %t0 = shl i32 -1, %nbits
- call void @use32(i32 %t0)
- %t1 = and i32 %t0, %data
- call void @use32(i32 %t1)
- %t2 = lshr i32 %t1, %nbits
- ret i32 %t2
-}
-
-; Non-canonical mask pattern. Let's just test a single case with all-extra uses.
-
-define i32 @t7_noncanonical_lshr_lshr_extrauses(i32 %data, i32 %nbits) {
-; CHECK-LABEL: @t7_noncanonical_lshr_lshr_extrauses(
-; CHECK-NEXT: [[T0:%.*]] = lshr i32 [[DATA:%.*]], [[NBITS:%.*]]
-; CHECK-NEXT: call void @use32(i32 [[T0]])
-; CHECK-NEXT: [[T1:%.*]] = shl i32 [[T0]], [[NBITS]]
-; CHECK-NEXT: call void @use32(i32 [[T1]])
-; CHECK-NEXT: [[T2:%.*]] = lshr i32 [[T1]], [[NBITS]]
-; CHECK-NEXT: ret i32 [[T2]]
-;
- %t0 = lshr i32 %data, %nbits
- call void @use32(i32 %t0)
- %t1 = shl i32 %t0, %nbits
- call void @use32(i32 %t1)
- %t2 = lshr i32 %t1, %nbits
- ret i32 %t2
-}
-
-define i32 @t8_noncanonical_lshr_ashr_extrauses(i32 %data, i32 %nbits) {
-; CHECK-LABEL: @t8_noncanonical_lshr_ashr_extrauses(
-; CHECK-NEXT: [[T0:%.*]] = lshr i32 [[DATA:%.*]], [[NBITS:%.*]]
-; CHECK-NEXT: call void @use32(i32 [[T0]])
-; CHECK-NEXT: [[T1:%.*]] = shl i32 [[T0]], [[NBITS]]
-; CHECK-NEXT: call void @use32(i32 [[T1]])
-; CHECK-NEXT: [[T2:%.*]] = ashr i32 [[T1]], [[NBITS]]
-; CHECK-NEXT: ret i32 [[T2]]
-;
- %t0 = lshr i32 %data, %nbits
- call void @use32(i32 %t0)
- %t1 = shl i32 %t0, %nbits
- call void @use32(i32 %t1)
- %t2 = ashr i32 %t1, %nbits
- ret i32 %t2
-}
-
-define i32 @t9_noncanonical_ashr_lshr_extrauses(i32 %data, i32 %nbits) {
-; CHECK-LABEL: @t9_noncanonical_ashr_lshr_extrauses(
-; CHECK-NEXT: [[T0:%.*]] = ashr i32 [[DATA:%.*]], [[NBITS:%.*]]
-; CHECK-NEXT: call void @use32(i32 [[T0]])
-; CHECK-NEXT: [[T1:%.*]] = shl i32 [[T0]], [[NBITS]]
-; CHECK-NEXT: call void @use32(i32 [[T1]])
-; CHECK-NEXT: [[T2:%.*]] = lshr i32 [[T1]], [[NBITS]]
-; CHECK-NEXT: ret i32 [[T2]]
-;
- %t0 = ashr i32 %data, %nbits
- call void @use32(i32 %t0)
- %t1 = shl i32 %t0, %nbits
- call void @use32(i32 %t1)
- %t2 = lshr i32 %t1, %nbits
- ret i32 %t2
-}
-
-define i32 @t10_noncanonical_ashr_ashr_extrauses(i32 %data, i32 %nbits) {
-; CHECK-LABEL: @t10_noncanonical_ashr_ashr_extrauses(
-; CHECK-NEXT: [[T0:%.*]] = ashr i32 [[DATA:%.*]], [[NBITS:%.*]]
-; CHECK-NEXT: call void @use32(i32 [[T0]])
-; CHECK-NEXT: [[T1:%.*]] = shl i32 [[T0]], [[NBITS]]
-; CHECK-NEXT: call void @use32(i32 [[T1]])
-; CHECK-NEXT: [[T2:%.*]] = ashr i32 [[T1]], [[NBITS]]
-; CHECK-NEXT: ret i32 [[T2]]
-;
- %t0 = ashr i32 %data, %nbits
- call void @use32(i32 %t0)
- %t1 = shl i32 %t0, %nbits
- call void @use32(i32 %t1)
- %t2 = ashr i32 %t1, %nbits
- ret i32 %t2
-}
-
-; Commutativity
-
-declare i32 @gen32()
-
-define i32 @t11_commutative(i32 %nbits) {
-; CHECK-LABEL: @t11_commutative(
-; CHECK-NEXT: [[DATA:%.*]] = call i32 @gen32()
-; CHECK-NEXT: [[T0:%.*]] = shl i32 -1, [[NBITS:%.*]]
-; CHECK-NEXT: [[T1:%.*]] = and i32 [[DATA]], [[T0]]
-; CHECK-NEXT: [[T2:%.*]] = lshr i32 [[T1]], [[NBITS]]
-; CHECK-NEXT: ret i32 [[T2]]
-;
- %data = call i32 @gen32()
- %t0 = shl i32 -1, %nbits
- %t1 = and i32 %data, %t0 ; swapped
- %t2 = lshr i32 %t1, %nbits
- ret i32 %t2
-}
-
-; Negative tests
-
-define i32 @n12(i32 %data, i32 %nbits) {
-; CHECK-LABEL: @n12(
-; CHECK-NEXT: [[T0:%.*]] = shl i32 2147483647, [[NBITS:%.*]]
-; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[DATA:%.*]]
-; CHECK-NEXT: [[T2:%.*]] = lshr i32 [[T1]], [[NBITS]]
-; CHECK-NEXT: ret i32 [[T2]]
-;
- %t0 = shl i32 2147483647, %nbits ; must be shifting -1
- %t1 = and i32 %t0, %data
- %t2 = lshr i32 %t1, %nbits
- ret i32 %t2
-}
-
-define i32 @n13(i32 %data, i32 %nbits0, i32 %nbits1) {
-; CHECK-LABEL: @n13(
-; CHECK-NEXT: [[T0:%.*]] = shl i32 -1, [[NBITS0:%.*]]
-; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[DATA:%.*]]
-; CHECK-NEXT: [[T2:%.*]] = lshr i32 [[T1]], [[NBITS1:%.*]]
-; CHECK-NEXT: ret i32 [[T2]]
-;
- %t0 = shl i32 -1, %nbits0
- %t1 = and i32 %t0, %data
- %t2 = lshr i32 %t1, %nbits1 ; different shift amounts
- ret i32 %t2
-}
-
-define i32 @n14(i32 %data, i32 %nbits0, i32 %nbits1, i32 %nbits2) {
-; CHECK-LABEL: @n14(
-; CHECK-NEXT: [[T0:%.*]] = lshr i32 [[DATA:%.*]], [[NBITS0:%.*]]
-; CHECK-NEXT: call void @use32(i32 [[T0]])
-; CHECK-NEXT: [[T1:%.*]] = shl i32 [[T0]], [[NBITS1:%.*]]
-; CHECK-NEXT: call void @use32(i32 [[T1]])
-; CHECK-NEXT: [[T2:%.*]] = lshr i32 [[T1]], [[NBITS2:%.*]]
-; CHECK-NEXT: ret i32 [[T2]]
-;
- %t0 = lshr i32 %data, %nbits0
- call void @use32(i32 %t0)
- %t1 = shl i32 %t0, %nbits1 ; different shift amounts
- call void @use32(i32 %t1)
- %t2 = lshr i32 %t1, %nbits2 ; different shift amounts
- ret i32 %t2
-}
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