[llvm] r365604 - [ARM] Enable VPUSH/VPOP aliases when either MVE or VFP is present

[Mikhail Maltsev via llvm-commits]

Author: miyuki
Date: Wed Jul 10 01:59:17 2019
New Revision: 365604

URL: http://llvm.org/viewvc/llvm-project?rev=365604&view=rev
Log:
[ARM] Enable VPUSH/VPOP aliases when either MVE or VFP is present

Summary:
Use the same predicates as VSTMDB/VLDMIA since VPUSH/VPOP alias to
these.

Patch by Momchil Velikov.

Reviewers: ostannard, simon_tatham, SjoerdMeijer, samparker, t.p.northover, dmgreen

Reviewed By: dmgreen

Subscribers: javed.absar, kristof.beyls, hiraditya, dmgreen, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64413

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
    llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
    llvm/trunk/test/MC/ARM/mve-fp-registers.s

Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=365604&r1=365603&r2=365604&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Wed Jul 10 01:59:17 2019
@@ -2591,7 +2591,7 @@ class NEONFPPat<dag pattern, dag result>
 // VFP/NEON Instruction aliases for type suffices.
 // Note: When EmitPriority == 1, the alias will be used for printing
 class VFPDataTypeInstAlias<string opc, string dt, string asm, dag Result, bit EmitPriority = 0> :
-  InstAlias<!strconcat(opc, dt, "\t", asm), Result, EmitPriority>, Requires<[HasVFP2]>;
+  InstAlias<!strconcat(opc, dt, "\t", asm), Result, EmitPriority>, Requires<[HasFPRegs]>;
 
 // Note: When EmitPriority == 1, the alias will be used for printing
 multiclass VFPDTAnyInstAlias<string opc, string asm, dag Result, bit EmitPriority = 0> {

Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=365604&r1=365603&r2=365604&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Wed Jul 10 01:59:17 2019
@@ -302,13 +302,13 @@ def VLSTM : AXSI4<(outs), (ins GPRnopc:$
 }
 
 def : InstAlias<"vpush${p} $r", (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r), 0>,
-                Requires<[HasVFP2]>;
+                Requires<[HasFPRegs]>;
 def : InstAlias<"vpush${p} $r", (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r), 0>,
-                Requires<[HasVFP2]>;
+                Requires<[HasFPRegs]>;
 def : InstAlias<"vpop${p} $r",  (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r), 0>,
-                Requires<[HasVFP2]>;
+                Requires<[HasFPRegs]>;
 def : InstAlias<"vpop${p} $r",  (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r), 0>,
-                Requires<[HasVFP2]>;
+                Requires<[HasFPRegs]>;
 defm : VFPDTAnyInstAlias<"vpush${p}", "$r",
                          (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r)>;
 defm : VFPDTAnyInstAlias<"vpush${p}", "$r",

Modified: llvm/trunk/test/MC/ARM/mve-fp-registers.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/mve-fp-registers.s?rev=365604&r1=365603&r2=365604&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/mve-fp-registers.s (original)
+++ llvm/trunk/test/MC/ARM/mve-fp-registers.s Wed Jul 10 01:59:17 2019
@@ -45,18 +45,50 @@ vldmia  r0, {d0}
 # FP32: vldmia  r0, {d0}               @ encoding: [0x90,0xec,0x02,0x0b]
 # NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers
 
+vpop    {d0-d15}
+# FP32: vpop {{.*}}                     @ encoding: [0xbd,0xec,0x20,0x0b]
+# NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers
+
+vpop.64    {d0-d15}
+# FP32: vpop {{.*}}                     @ encoding: [0xbd,0xec,0x20,0x0b]
+# NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers
+
 vstmia  r0, {d0}
 # FP32: vstmia  r0, {d0}                @ encoding: [0x80,0xec,0x02,0x0b]
 # NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers
 
+vpush    {d0-d15}
+# FP32: vpush {{.*}}                    @ encoding: [0x2d,0xed,0x20,0x0b]
+# NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers
+
+vpush.64    {d0-d15}
+# FP32: vpush {{.*}}                    @ encoding: [0x2d,0xed,0x20,0x0b]
+# NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers
+
 vldmia  r0, {s0}
 # FP32: vldmia  r0, {s0}                @ encoding: [0x90,0xec,0x01,0x0a]
 # NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers
 
+vpop {s0-s31}
+# FP32: vpop {{.*}}                     @ encoding: [0xbd,0xec,0x20,0x0a]
+# NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers
+
+vpop.32 {s0-s31}
+# FP32: vpop {{.*}}                     @ encoding: [0xbd,0xec,0x20,0x0a]
+# NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers
+
 vstmia  r0, {s0}
 # FP32: vstmia  r0, {s0}                @ encoding: [0x80,0xec,0x01,0x0a]
 # NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers
 
+vpush {s0-s31}
+# FP32: vpush {{.*}}                    @ encoding: [0x2d,0xed,0x20,0x0a]
+# NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers
+
+vpush.32 {s0-s31}
+# FP32: vpush {{.*}}                    @ encoding: [0x2d,0xed,0x20,0x0a]
+# NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers
+
 fldmdbx r0!, {d0}
 # FP32: fldmdbx r0!, {d0}               @ encoding: [0x30,0xed,0x03,0x0b]
 # NOFP32: :[[@LINE-2]]:{{[0-9]+}}: {{note|error}}: instruction requires: fp registers